Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Proceedings ArticleDOI
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
TL;DR: Postlayout simulations have demonstrated that circuits designed according to the suggested strategy, can achieve a delay reduction compared to conventional CMOS designs, whereas the energy consumption can be reduced down to 46% compared to DTMOS solutions, for a supply voltage of 0.4V.
Journal ArticleDOI
Evaluation of the differential capacitance for ferroelectric materials using either charge-based or energy-based expressions
TL;DR: Differential capacitance is derived based upon energy, charge or current considerations, and determined when it may go negative or positive as discussed by the authors, and conditions when the differential capacitance might go negative in relation to the static capacitance are shown.
Journal ArticleDOI
Implementation of Transistor Stacking Technique in Combinational Circuits
Ankita Nagar,Vidhu Parmar +1 more
TL;DR: It is found that when the number of low-input increases in case of NAND gate the power dissipation decreases but the delay increases and for NOR gate power Dissipation decreases with the increase in high input vector combinations.
Proceedings ArticleDOI
Impact of technology scaling on leakage reduction techniques
TL;DR: In this article, the impact of stack forcing, pin reordering, reverse body biasing and high threshold voltage transistors on the performance and noise margins of logic gates in the 65 nm, 45 nm, and 32 nm nodes are simulated and analyzed.
Patent
Leakage power reduction in CMOS circuits
TL;DR: In this paper, the source and drain regions of a field effect transistor are formed in insulating pockets that cause the source region and drain region to be electrically isolated from the substrate, thereby minimizing junction capacitance and device crosstalk.
References
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TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.