Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Journal ArticleDOI
Benchmarking Digital Die-to-Die Channels in 2.5-D and 3-D Heterogeneous Integration Platforms
TL;DR: Compact circuit models and HSPICE simulations are used to benchmark die-to-die communication channels in 2.5-D and 3-D heterogeneous integration platforms and observe that advanced process technologies must be integrated with smaller physical I/O dimensions and shorter wire lengths to attain full advantages of scaling.
Journal ArticleDOI
Leakage Models for High-Level Power Estimation
TL;DR: This work presents RT level leakage macro models, which are faster than recent gate level models, while preserving the accuracy of the transistor level models to a great extent, and describes the subthreshold, gate, and junction leakage of recent technology devices.
Proceedings ArticleDOI
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
TL;DR: A novel system level temperature aware and floorplan aware leakage power estimator, STEFAL, is proposed, which considers both the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating the leakage power.
Proceedings ArticleDOI
Effects of temperature on electrical parameters in GaAs SOI FinFET and application as digital inverter
TL;DR: In this paper, a GaAs SOI (Silicon on insulator) FinFET is proposed and the impact of temperature on electron mobility, drain current, and Ion/Ioff have been reported.
Proceedings ArticleDOI
Improving the Detectability of Resistive Open Faults in Scan Cells
TL;DR: The newly proposed method includes application of tests at higher temperatures and modifications to an earlier proposed flush test to augment earlier test methods to detect internal scan chain opens with a wider range of resistances.
References
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TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
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Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
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Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.