Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Journal ArticleDOI
Variability-aware architecture level optimization techniques for robust nanoscale chip design
TL;DR: A novel process variation aware statistical RTL optimization approach is presented, which gives a relative and integrated perspective of various power-performance tradeoffs against the baseline case, thus serving as a guideline to help designers make appropriate decisions.
Journal ArticleDOI
Review of Leakage Power Reduction in CMOS Circuits
TL;DR: This paper mainly focuses on the review of various works done in this field and a review of recent work done on a new technique LSSR (Lector Stack State Retention Technique) is discussed in the paper.
Low-Power Clocking and Circuit Techniques for Leakage and Process Variation Compensation
TL;DR: In this article, an energy recovering clocking technique aimed at reducing the total chip clock power is presented, based on theoretical analysis the technique is shown to enable considerable clock power savings, and the impact of the proposed technique on conventional flip-flop topologies is studied.
Dissertation
Balancing energy, security and circuit area in lightweight cryptographic hardware design
TL;DR: This thesis addresses lightweight hardware design and countermeasures to improve cryptographic computation to deal with the increasing amount of processing data without compromising the overall security.
Proceedings ArticleDOI
A dual-level adaptive supply voltage system for variation resilience
TL;DR: This work proposes a dual-level ASV (dual-ASV) system for designs containing many timing critical paths that can simultaneously provide ASV at both coarse- grained and fine-grained levels, and has limited power routing overhead.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.