Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
More filters
Proceedings ArticleDOI
A comparative analysis of coarse-grain and fine-grain power gating for FPGA lookup tables
TL;DR: It is found that power-gating can be employed to drastically reduce the leakage power dissipation in the SRAM and more leakage savings were obtained with coarse-grain power- gating than with fine- grain power gating.
Proceedings ArticleDOI
A low-power dual-clock strategy for digital circuits of EPC Gen2 RFID tag
TL;DR: A dual-clock strategy with both 1.28 and 2.56 MHz clocks for the digital circuits of EPC Gen2 tag is developed and an error shift approach is proposed to reduce the backscatter link frequency (BLF) errors.
Journal ArticleDOI
Comparison of Total-Ionizing-Dose Effects in Bulk and SOI FinFETs at 90 and 295 K
T. D. Haeffner,R. F. Keller,Rong Jiang,Brian D. Sierawski,Michael W. McCurdy,En Xia Zhang,R. W. Mohammed,Dennis R. Ball,Michael L. Alles,Robert A. Reed,Ronald D. Schrimpf,Daniel M. Fleetwood +11 more
TL;DR: In this article, both bulk and silicon-on-insulator (SOI) n-channel FinFETs with fin widths of 15-40 nm and channel lengths of 45 and 1000 nm were irradiated with 1.8 MeV protons.
Journal ArticleDOI
A new approach to power estimation and reduction in CMOS digital circuits
Ireneusz Brzozowski,Andrzej Kos +1 more
TL;DR: A procedure of combinational circuit optimization for power dissipation reduction has been developed and results of the power estimation received for some benchmark circuits are much closer to SPICE simulations than values obtained for other methods.
Journal ArticleDOI
A Nano junctionless Double-Gate MOSFET by Using the Charge Plasma Concept to Improve Short-Channel Effects and Frequency Characteristics
TL;DR: In this paper, a junctionless double-gate metal-oxide semiconductor field effect transistor (MOSFET) is investigated by using the concept of charge plasma, which can improve some electrical parameters.
References
More filters
Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Book
Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.