Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Proceedings ArticleDOI
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units
TL;DR: In this paper, the limitations of the static sleep signal generation approach are identified, and the use of a dynamic alternative that is capable of adopting the counter length to the running application is proposed.
Journal ArticleDOI
A 0.065-mm 3 Monolithically-Integrated Ultrasonic Wireless Sensing Mote for Real-Time Physiological Temperature Monitoring
TL;DR: A device for real-time in vivo temperature monitoring that relies on “chip-as-system” integration with an on-chip piezoelectric transducer and an Allan deviation floor of <138.6 ppm is presented, indicating the feasibility of using the mote for continuous physiological temperature monitoring.
Journal ArticleDOI
A 0.6-V Delta–Sigma Modulator With Subthreshold-Leakage Suppression Switches
TL;DR: A 0.6-V 34-muW delta-sigma modulator implemented by using a standard 0.13-mum complementary metal-oxide-semiconductor technology and a high-performance low-quiescent amplifier architecture is developed for the modulator, which achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak Signal-To-Noise-plus-distortion ratio of 81 dB.
Proceedings ArticleDOI
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
TL;DR: In this article, the authors proposed an efficient technique to reduce both dynamic and static power dissipation in scan structures, where scan cell outputs which are not on the critical path(s) are multiplexed to fixed values during scan mode.
Journal ArticleDOI
CMOS IC technology scaling and its impact on burn-in
TL;DR: In this paper, the effect of junction temperature on device reliability, aging, and burn-in procedure optimization is discussed, as well as the impact of device thermal runaway and the requirements it forces on commercial burnin ovens, device package and device cooling.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Book
Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.