Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Journal ArticleDOI
Improvement of n-channel metal-oxide-semiconductor transistors by tensile stress despite increase in both on and subthreshold off currents
TL;DR: In this article, the authors found that tensile stress actually increases both the on current and the sub-threshold off current for n-channel metal-oxide-semiconductor transistors because of an increase in mobility.
Design of Ultra-Low-Power Analog-to-Digital Converters
TL;DR: Power consumption is one of the main design constraints in today’s integrated circuits for systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices.
Proceedings ArticleDOI
Arithmetic and architectural design to reduce leakage in nano-scale digital circuits
TL;DR: Techniques to reduce thestatic power consumption in digital applications for nano-scale CMOS technologies are addressed and a 79% arithmetic reduction of the static power consumption is indicated, by using serial arithmetic instead of bit-parallel.
Leakage reduction using power gating techniques in sram sense amplifiers
Deepak Mittal,T. Vigneswaran +1 more
TL;DR: In this article, the authors have focused on memory leakage power reduction particularly in sense amplifiers using Fine Grain Power Gating (FGPG), Variable Body Biasing Technique (VBBT), Proposed Different Footer Dual Stack Technique (FDST) based both PMOS, one PMOS and one NMOS, both NMOS and Proposed PMOS Footer Triple Stack technique (PFTST) in Current Sense Amplifier (CSA), Charge Transfer Sense Amplifiers (CTSA), and High Speed Sense Amplifer (HSSA).
Posted ContentDOI
Energy Efficient Tri-State CNFET Ternary Logic Gates
TL;DR: A novel method to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs) and results show that the two-digit adder/subtractor using the proposed gates has 12X and 5X lower power consumption and PDP respectively, compared to previous designs.
References
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TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
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Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.