Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Proceedings ArticleDOI
Modeling temperature distribution in Networks-on-Chip using RC-circuits
TL;DR: To simulate the dynamic nature of temperature, the thermal properties of according integrated systems are modeled through the instantiation of equivalent RC-circuits through the dualism between electrical and thermal flows of energy.
Proceedings ArticleDOI
Low-power SRAMs power mode control logic: Failure analysis and test solutions
L. B. Zordan,Alberto Bosio,Luigi Dilillo,Patrick Girard,A. Todri,Arnaud Virazel,N. Badereddine +6 more
TL;DR: This paper provides a detailed analysis based on electrical simulations to characterize the impact of resistive-open defects on the power mode control logic and introduces appropriate fault models that represent the observed faulty behaviors.
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Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions
TL;DR: This review paper discusses timingclosure problem explaining the root cause of its difficulty, and explains traditional techniques that address timing closure problem.
Journal ArticleDOI
Efficient testing and diagnosis of faulty power switches in SOCs
TL;DR: The use of power switches in modern system chips (SOCs) is inevitable as they allow for efficient on-chip static power management and the proposed method allows for the testing of on/off functionality.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.