Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Proceedings ArticleDOI
A 1280×960 Dynamic Vision Sensor with a 4.95-μm Pixel Pitch and Motion Artifact Minimization
Yunjae Suh,Choi Seungnam,Ito Masamichi,Jeong-Seok Kim,Young-Ho Lee,Jong-Seok Seo,Jung Hee-Jae,Yeo Dong-Hee,Seol Namgung,Bong Jongwoo,Sehoon Yoo,Seung-Hun Shin,Doo-Won Kwon,Pil-Kyu Kang,Seok-Ho Kim,Hoon-joo Na,Ki-Hyun Hwang,Chang-Woo Shin,Junseok Kim,Paul K. J. Park,Joonseok Kim,Hyunsurk Ryu,Yongin Park +22 more
TL;DR: This paper reports a 1280×960 DVS with in-pixel Cu-Cu connection and the newly designed GIDL-suppression scheme that achieves a 4.95-μm pixel pitch with a sequential column selection scheme and a global event-holding function to minimize motion artifacts.
Journal ArticleDOI
Characterization of Single Bit and Multiple Cell Soft Error Events in Planar and FinFET SRAMs
Yi-Pin Fang,Anthony S. Oates +1 more
TL;DR: It is shown that high-energy neutron-induced MCU events are determined by charge sharing among adjacent cells and are sensitive to both transistor drain area and the details of the process technology used, via the dependence of charge mobility on the substrate doping level.
Journal ArticleDOI
Managing subthreshold leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)
TL;DR: In this paper, the analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits.
Journal ArticleDOI
FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices
TL;DR: It is proved that the FinSAL S-box circuit is resistant to a DPA attacks through a developed DPA attack flow applicable to SPICE simulations, and FinSal gates at 14-nm FinFET offer superior security with optimum power consumption, therefore is the best candidate to design low-power secure IoT devices.
Journal ArticleDOI
High temperature gate-bias and reverse-bias tests on SiC MOSFETs
Li Yang,Alberto Castellazzi +1 more
TL;DR: In this paper, gate bias stress induced threshold voltage instability and leakage current degradation resulted from drain-source reverse bias stress at elevated temperature is investigated and reported, and the HTGB and HTRB tests are performed in this work to characterise gate-oxide integrity and verify junction and termination robustness.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.