Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
More filters
Journal ArticleDOI
A two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions
TL;DR: In this article, a two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions (STT-MTJs) is proposed that is smaller than the conventional ones with equivalent performance.
Journal ArticleDOI
Analysis of the Effect of Temperature Variations on Sub-threshold Leakage Current in P3 and P4 SRAM Cells at Deep Sub-Micron CMOS Technology
TL;DR: It has been observed that the sub-threshold leakage and the standby power dissipation increases with increase in temperature, however, due to the stacked pMOS design used in P4 and P3 SRAM cells, minimumSub-th threshold leakage and standby leakage power is observed as compared to the conventional 6T design.
Proceedings ArticleDOI
Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devices
TL;DR: This work proposes a low power in-memory computing platform using a novel 4-terminal magnetic domain wall motion (4T-DWM) device, in which the proposed 4T- DWM device can be employed as both non-volatile memory cell and in- memory logic.
Dissertation
Développement d'architectures 3D à base de transistors MOS à canal nanofil III-V
TL;DR: In this article, the authors propose a 3D nanofils verticaux III-V for the realisation of transistors MOS, presenting ainsi des challenges qu'au niveau de canal.
Proceedings ArticleDOI
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing
TL;DR: In this article, a scalable algorithm for tightening upper bound computation, with a controlled and tunable computational cost, is proposed, leveraging the capabilities of state-of-the-art commercial timing analysis engines, and it is tightly integrated into standard industrial flow for leakage optimization.
References
More filters
Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Book
Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.