Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Proceedings ArticleDOI
Design high performance and low power 10T full adder cell using double gate MOSFET at 45nm technology
TL;DR: The used parameters value has been varied significantly thus improving the performance of full adder, and Power Gating technique achieves 93% reduction of leakage current, active power and delay as compared with conventional double gate full adders.
Proceedings ArticleDOI
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control
Hao Xu,Wen-Ben Jone,Ranga Vemuri +2 more
TL;DR: Two novel techniques are proposed, workload-adaptive Vth hopping (WAVTH) and hierarchical Vth hopped (HIVTH), to tackle the overhead problems and enable aggressive runtime leakage control.
Proceedings ArticleDOI
Double edge triggered Feedback Flip-Flop in sub 100NM technology
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Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices
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Low-Power Integrated Circuit Design for Wearable Biopotential Sensing
TL;DR: In this article, the authors present an overview of the fundamentals and state-of-the-art in non-invasive biopotential recording instrumentation with a focus on micropower-integrated circuit design for high-density and unobtrusive wearable applications.
References
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Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
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Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.