Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Proceedings ArticleDOI
Generating power-hungry test programs for power-aware validation of pipelined processors
TL;DR: This paper demonstrates the actual difficulty of assembling power-hungry test programs on pipelined processors and proposes an automated methodology, based on an automatic optimizer, that allows a push-bottom generation of high-power consuming programs under user-defined constraints.
Journal ArticleDOI
Exploiting Gate Leakage in Deep-Submicrometer CMOS for Input Offset Adaptation
TL;DR: An adaptive device is presented that exploits gate leakage in the 90-nm STM CMOS process for offset cancellation at its input by a high-pass-filtering input stage with a very low cutoff due to a time constant of approximately 130 ms.
Journal ArticleDOI
A Gate Leakage Feedback Element in an Adaptive Amplifier Application
TL;DR: The feedback element has very high nonlinear impedance from about 100 M to several gigaohms depending on the applied voltage, and is suitable for adaptive applications where long time constants are required and small, slowly wandering offsets can be tolerated.
Proceedings ArticleDOI
A novel leakage power reduction technique for nano-scaled CMOS digital integrated circuits
TL;DR: In proposed method, gate length biasing is combined with progressive sizing and greatly reduces both the leakage power consumption and its spread without a significant delay overhead.
Certain Investigations on Static Power Dissipation in various Nano-Scale CMOS D Flip-Flop Structures
TL;DR: In this article, the impact of existing leakage current reduction techniques on various D Flip Flop Circuits are analyzed and summarized, and the same leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.