Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Journal ArticleDOI
An ultra-low leakage synaptic scaling homeostatic plasticity circuit with configurable time scales up to 100 kilo-seconds
TL;DR: In this paper, the authors present an ultra-low leakage circuit, integrated into an automatic gain control scheme, that can implement the synaptic scaling homeostatic process over extremely long time scales.
Proceedings ArticleDOI
A Pattern Generation Technique for Maximizing Power Supply Currents
TL;DR: A Current Maximizing Pattern Generation (CMPG) algorithm is proposed which greatly reduces the computational complexity by using a parameterized branch-and-bound heuristic that prunes the search space by looking for a lower as well as an upper bound for maximum switching currents.
Journal ArticleDOI
Variability-Aware Bulk-MOS Device Design
Javid Jaffari,Mohab Anis +1 more
TL;DR: A novel device optimization methodology is presented that incorporates variability awareness into the device-design flow such that the designed device satisfies desired bounds on total leakage, saturation current, and intrinsic delay under parameter variabilities.
Journal ArticleDOI
Accumulated body ultranarrow channel silicon transistor with extreme threshold voltage tunability
Ali Gokirmak,Sandip Tiwari +1 more
TL;DR: A side-gated ultranarrow channel (width <10nm) silicon field effect transistor (FET) with extreme threshold voltage (Vt) tunability is described in this article.
Book ChapterDOI
Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning
TL;DR: In this paper, the power savings that can be expected, the power-delay trade-offs, and the implications of adaptive voltage scaling (AVS) and adaptive body biasing (ABB) on present semiconductor technologies are discussed.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.