Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Energy-precision tradeoffs in the graphics pipeline
TL;DR: This dissertation proposes to lower the energy consumption of GPUs by reducing the precision of floating-point arithmetic in the graphics pipeline and the data sent and stored on- and off-chip, and develops an energy model for GPUs.
Proceedings Article
A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments.
TL;DR: This work presents a novel architecture, which is both device and circuit independent, and a constructive solution for Kolmogorov's superposition and (multi-threshold) threshold logic synthesis could be used for automating the design.
Proceedings ArticleDOI
4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS
TL;DR: This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2 PASCL circuit technology.
Patent
Power gating various number of resources based on utilization levels
TL;DR: In this article, the power-gating circuit resources of an integrated circuit are associated into sets responsive to utilization levels and the associating includes providing a first set of the sets, a first number of the circuit resources in the first set being associated with a first level of utilization.
Journal ArticleDOI
Techniques for low leakage nanoscale vlsi circuits: a comparative study
TL;DR: This article has analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at different technology nodes in active as well as standby modes and comparative results and discussion of different leakage reduction techniques are very useful to illustrate the effective technique in active and standby modes.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Book
Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.