Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Proceedings ArticleDOI
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits
Armin Tajalli,Yusuf Leblebici +1 more
TL;DR: This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits.
Journal ArticleDOI
P 2 NoC: Power- and Performance-aware NoC Architectures for Sustainable Computing
TL;DR: A Power- and Performance-aware NoC (P 2 NoC) architecture that power gates router elements and WIs depending upon their utilization to reduce leakage power and provides a flexible sustainable computing platform that can be optimized for a wide range of application scenarios.
Book ChapterDOI
Device physics, modeling, and technology for nano-scaled semiconductor devices
TL;DR: In this paper, the authors introduce the device physics, modeling, and technology for the different silicon-based device structures, and the possibility to make use of CMOS fabrication steps for 3D Si die stacking is discussed.
Journal ArticleDOI
Impact of Iterative Deuterium Annealing in Long-Channel MOSFET Performance
Dongmei Wang,Ja-Yun Ku,Dae Han Jung,Khwang-Sun Lee,Woo-Cheol Shin,Byung-Do Yang,Jun-Young Park +6 more
TL;DR: In this article , the authors demonstrate the iterative impact of high pressure deuterium annealing (HPD) for the better fabrication of semiconductor devices and provide an HPD condition that maximizes on-state current (ION) but minimizes off-state currents (IOFF).
Power Optimization and Prediction Techniques for FPGAs
TL;DR: Two novel computer-aided design techniques for FPGA leakage power reduction are presented, which are unique in that they substantially reduce leakage power, while imposing no cost, meaning that they have no impact on FPGAs area-efficiency, speed, or fabrication cost.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Book
Physics and technology of semiconductor devices
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.