Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Journal ArticleDOI
Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM
TL;DR: Experimental results in a 46 nm DRAM technology indicated that the data retention time provided by the proposed biasing control scheme is improved by up to 60% as compared to the conventional fixed biasing scheme.
Journal ArticleDOI
Low standby leakage 12T SRAM cell characterisation
TL;DR: In this paper, a low power and variability-aware static random access memory (SRAM) architecture based on a twelve-transistor (12T) cell is proposed, which obtains low static power dissipation due to a parallel global latch and storage latch, along with a global wordline.
Journal ArticleDOI
Computational modeling of process induced damage during plasma clean
TL;DR: In this article, a suite of computational models is used to investigate damage to ultrathin (1.0-5.5nm) transistor gate dielectric (SiO2) during Ar∕O2 based plasma cleaning in a capacitively coupled plasma reactor.
Proceedings ArticleDOI
Measuring Leakage Power in Nanometer CMOS 6T-SRAM Cells
TL;DR: This work develops the design of a 6T-SRAM cell utilizing two semiconductor technologies and a range of circuit design parameters to provide design guidelines for leakage power-aware digital systems.
Power Amplifier Circuits in CMOS Technologies
TL;DR: The wireless market has experienced a remarkable development and growth since the introduction of the first mobile phone systems as discussed by the authors, with a steady increase in the number of subscribers, new applicatio...
References
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Book
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