Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
Kaushik Roy,Saibal Mukhopadhyay,H. Mahmoodi-Meimand +2 more
- Vol. 91, Iss: 2, pp 305-327
TLDR
Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.Abstract:
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.read more
Citations
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Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags
TL;DR: This paper provides an architectural technique which exploits the fact that many applications process a large number of zero data and appends additional flags in cache tag arrays and set these additional bits if the corresponding data in the cache line is the zero-valued data in which all data bits are zero.
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High-Quality Thin SiO2 Films Grown by Atomic Layer Deposition Using Tris(dimethylamino)silane (TDMAS) and Ozone
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Advancement in nanoscale CMOS device design en route to ultra-low-power applications
TL;DR: This paper attempts to categorize the challenges and solutions for low-power and low-voltage application and thus provides a roadmap for device designers working in the submicron and deep submicrons region of CMOS devices separately.
Proceedings ArticleDOI
A dual dielectric approach for performance aware gate tunneling reduction in combinational circuits
TL;DR: This paper proposes a new approach called dual dielectrics of dual thicknesses (DKDT) for the reduction of both ON and OFF state gate tunneling currents, and claims that the simultaneous utilization of SiON and SiO/sub 2/ each with multiple thicknesses is a better approach for gate leakage reduction.
Proceedings ArticleDOI
NBTI-aware data allocation strategies for scratchpad memory based embedded systems
TL;DR: It is demonstrated how intelligent software directed data allocation strategies can extend the lifetime of partitioned SPMs by means of distributing the idleness across the memory sub-banks.
References
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Book
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Yuan Taur,Tak H. Ning +1 more
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TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.