Showing papers on "Silicon on insulator published in 2005"

Nanophotonic waveguides in silicon-on-insulator fabricated with CMOS technology

Abstract: High-index-contrast, wavelength-scale structures are key to ultracompact integration of photonic integrated circuits. The fabrication of these nanophotonic structures in silicon-on-insulator using complementary metal-oxide-semiconductor processing techniques, including deep ultraviolet lithography, was studied. It is concluded that this technology is capable of commercially manufacturing nanophotonic integrated circuits. The possibilities of photonic wires and photonic-crystal waveguides for photonic integration are compared. It is shown that, with similar fabrication techniques, photonic wires perform at least an order of magnitude better than photonic-crystal waveguides with respect to propagation losses. Measurements indicate propagation losses as low as 0.24 dB/mm for photonic wires but 7.5 dB/mm for photonic-crystal waveguides.

Beyond the Rayleigh scattering limit in high-Q silicon microdisks: theory and experiment.

Abstract: Using a combination of resist reflow to form a highly circular etch mask pattern and a low-damage plasma dry etch, high-quality-factor silicon optical microdisk resonators are fabricated out of silicon-on-insulator (SOI) wafers. Quality factors as high as Q = 5×10^6 are measured in these microresonators, corresponding to a propagation loss coefficient as small as α ~ 0.1 dB/cm. The different optical loss mechanisms are identified through a study of the total optical loss, mode coupling, and thermally-induced optical bistability as a function of microdisk radius (5-30 µm). These measurements indicate that optical loss in these high-Q microresonators is limited not by surface roughness, but rather by surface state absorption and bulk free-carrier absorption.

Design and fabrication of a hybrid silicon three-axial force sensor for biomechanical applications

Abstract: This paper presents the design and development of a silicon-based three-axial force sensor to be used in a flexible smart interface for biomechanical measurements. Normal and shear forces are detected by combining responses from four piezoresistors obtained by ion implantation in a high aspect-ratio cross-shape flexible element equipped with a 525 m high silicon mesa. The mesa is obtained by a subtractive dry etching process of the whole handle layer of an SOI wafer. Piezoresistor size ranges between 6 and 10m in width, and between 30 and 50m in length. The sensor configuration follows a hybrid integration approach for interconnection and for future electronic circuitry system integration. The sensor ability to measure both normal and shear forces with high linearity ( ∼99%) and low hysteresis is demonstrated by means of tests performed by applying forces from 0 to 2 N. In this paper the packaging design is also presented and materials for flexible sensor array preliminary assembly are described. © 2005 Elsevier B.V. All rights reserved.

A sub-micron depletion-type photonic modulator in Silicon On Insulator.

Abstract: We provide detailed analysis of a four terminal p+pnn+ optical modulator integrated into a silicon-on-insulator (SOI) rib waveguide. The proposed depletion device has been designed to approach birefringence free operation. The modulation mechanism is the carrier depletion effect in a pn junction; carrier losses induced are minimised in our design and because we use a depletion device, the device is insensitive to carrier lifetime. The rise time and fall time of the proposed device have both been calculated to be 7 ps for a reverse bias of only 5 volts. A maximum excess loss of 2 dB is predicted for TE and TM due to the presence of p type and n type carriers in the waveguide.

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

Abstract: A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.

Lifetime of photogenerated carriers in silicon-on-insulator rib waveguides

Abstract: The lifetime of photogenerated carriers in silicon-on-insulator rib waveguides is studied in connection with the optical loss they produce via nonlinear absorption. We present an analytical model as well as two-dimensional numerical simulation of carrier transport to elucidate the dependence of the carrier density on the geometrical features of the waveguide. The results suggest that effective carrier lifetimes of ⩽1ns can be obtained in submicron waveguides resulting in negligible nonlinear absorption. It is also shown that the lifetime and, hence, carrier density can be further reduced by application of a reverse bias pn junction.

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

Abstract: We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.

Optical bistability and pulsating behaviour in Silicon-On-Insulator ring resonator structures.

Abstract: We demonstrate optical bistability in a Silicon-On-Insulator two-bus ring resonator with input powers as low as 0.3mW. We evaluate the importance of the different nonlinear contributions and derive time constants for carrier and thermal relaxation effects. In some cases, we also observe pulsation due to interaction between the dominant nonlinear effects. Such a behaviour may be problematic for possible memory and switching operations. Alternatively, it could be used for (tunable) pulse generation.

A compact silicon-on-insulator polarization splitter

Abstract: A compact directional coupler-based polarization splitter is designed and realized using silicon-on-insulator (SOI) waveguides. Even though silicon does not have any material birefringence, the high index contrast obtained in the SOI platform and reduced waveguide dimensions makes it possible to induce significant birefringence. Polarization splitting is achieved by making use of this geometry-induced birefringence. In this work, we demonstrate polarization splitting in devices as short as 120 /spl mu/m. Even smaller devices can be made using submicron-thick Si waveguides.

Integrated polarization beam splitter in high index contrast silicon-on-insulator waveguides

Abstract: We design, fabricate, and test a novel transverse-electric/transverse-magnetic (TE/TM) polarization beam splitter which is based on the dependence of birefringence on rib width in silicon-on-insulator waveguides. The polarization beam splitter has high TE to TM extinction ratio, low excess loss and wide operation bandwidth. The simple fabrication method involves only single etch step.

Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

Abstract: We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers

Silicon-on-insulator chip with multiple crystal orientations

Abstract: A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the silicon-on-insulator chip also includes a first transistor of a first conduction type formed on the first silicon island, and a second transistor of a second conduction type formed on the second silicon island. For example, the first crystal orientation can be (110) while the first transistor is a p-channel transistor, and the second crystal orientation can be (100) while the second transistor is an n-channel transistor.

Bonded planar double-metal-gate NMOS transistors down to 10 nm

Abstract: Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

Monolithic MEMS quadrupole mass spectrometers by deep silicon etching

Abstract: A wafer-scale, batch fabrication process for constructing quadrupole mass spectrometers using microelectromechanical systems (MEMS) technology is described. The device is formed from two bonded silicon-on-insulator (BSOI) substrates, which are attached together to form a monolithic block. Deep etched features and springs formed in the outer silicon layers are used to locate cylindrical metal electrode rods, while similar features formed in the inner silicon layers are used to define integrated ion entrance and exit optics. The precision of the assembly is determined by lithography and deep etching, and by the mechanical definition of the bonded silicon layers. Mass filtering is demonstrated, with a mass range of /spl ap/ 400 a.m.u. and a mass resolution of 1 a.m.u. at 219 a.m.u., using quadrupoles with rods of 500 /spl mu/m diameter and 30 mm length, operating at 6 MHz RF frequency.

Birefringence control using stress engineering in silicon-on-insulator (SOI) waveguides

Abstract: We demonstrate that stress engineering is an effective tool to modify or eliminate polarization dispersion in silicon-on-insulator (SOI) waveguide devices, for a wide range of waveguide cross-section shapes and dimensions. The stress-induced effects on the modal birefringence of SOI waveguides are investigated numerically and experimentally. Finite-element simulations show that while the birefringence of ridge waveguides with both slanted and vertical sidewalls can be effectively modified using cladding stress, the birefringence becomes much less sensitive to dimension fluctuations with decreasing sidewall slope. To efficiently simulate the stress-induced effects we propose a normalized plane-strain model which can achieve comparable accuracy as a fully generalized plane-strain model but requires significantly less computational resources. Excellent agreement is achieved between the calculated and measured birefringence tuning using SiO/sub 2/ cladding induced stress. Finally, both calculations and experiments confirm that cladding induced stress can be used to eliminate the birefringence in SOI waveguides of arbitrary shapes, for typical SiO/sub 2/ film stress values (/spl sigma//sub film//spl ap/-100 to -300 MPa) and cladding thicknesses of the order of 1 /spl mu/m or less.

Silicon waveguide-integrated optical power monitor with enhanced sensitivity at 1550nm

Abstract: We describe the fabrication and operation of an optical power monitor, monolithically integrated with a silicon-on-insulator rib waveguide. The device consists of a p+‐v‐n+ structure with a detection volume coincident with the single-mode supporting waveguide. Detection of optical signals at wavelengths around 1550nm is significantly enhanced by the introduction of midband-gap generation centers, which provide partial absorption of the infrared light. The most efficient device extracted 19% of optical power from the waveguide and showed a responsivity of 3mA∕W. These devices are fabricated using current standard processing technology and are fully compatible with silicon waveguide technology and integrated operational amplifier circuits.

Integration of InP/InGaAsP photodetectors onto silicon-on-insulator waveguide circuits

Abstract: The integration of optical functionalities on a chip has been a long standing goal in the optical community. Given the call for more integration, Silicon-on-Insulator (SOI) is a material system of great interest. Although mature CMOS technology can be used for the fabrication of passive optical functionality, particular photonic functions like efficient light emission still require III-V semiconductors. We present the technology for heterogeneous integration of III-V semiconductor optical components and SOI passive optical components using benzocyclobutene (BCB) die to wafer bonding. InP/InGaAsP photodetectors on SOI waveguide circuits were fabricated. The developed process is compatible with the fabrication of InP/InGaAsP light emitters on SOI.

The state-of-the-art of silicon-on-sapphire CMOS RF switches

Abstract: Silicon-on-Sapphire (SOS) CMOS FETs have many properties which are desirable for RF switch applications. By being manufactured on an insulating sapphire substrate, the bulk parasitic capacitances typical of CMOS FETs are eliminated. The SOS FET has a very low Ron-Coff product, allowing for low insertion loss and high isolation in high frequency applications. Despite the low breakdown voltage intrinsic to Si, SOS FETs can be stacked in series to withstand high voltages when biased in subthreshold. This work studies the tradeoffs of SOS RF switch design and compares SOS against other technologies such as GaAs and Si-based SOI. Also presented is a high power SP6T switch with insertion loss of 0.6 dB at 2 GHz and isolation of 40 dB at 2 GHz. The presented switch has the highest linearity reported to date of any SP6T switch with a P1dB of 20 W and OIP3 of <+70 dBm.

Direct measurement of transient pulses induced by laser and heavy ion irradiation in deca-nanometer devices

Abstract: This paper investigates the transient response of 50-nm gate length fully and partially depleted SOI and bulk devices to pulsed laser and heavy ion microbeam irradiations. The measured transient signals on 50-nm fully depleted devices are very short, and the collected charge is small compared to older 0.25-/spl mu/m generation SOI and bulk devices. We analyze in detail the influence of the SOI architecture (fully or partially depleted) on the pulse duration and the amount of bipolar amplification. For bulk devices, the doping engineering is shown to have large effects on the duration of the transient signals and on the charge collection efficiency.

Planar substrate devices integrated with finfets and method of manufacture

Abstract: A planar substrate device (100) integrated with fin field effect transistors (FinFETs) and a method of manufâcture comprises a silicon-on-insulator (SOI) wafer (101) comprising a substrate (103); a buried insulator layer (105) over the substrate (103); and a semiconductor layer (115) over the buried insulator layer (105). The structure (100) further comprises a FinFET (130) over the buried insulator layer (105) and a field effect transistor (FET) (131) integrated in the substrate (103), wherein the FET (127) gate is planar to the FinFET gate (125). The structure (100) further comprises retrograde well regions (104, 106, 108, 110) configured in the substrate (103). In one embodiment, the structure (100) further comprises a shallow trench isolation region (111) configured in the substrate (103).

Embedded slanted grating for vertical coupling between fibers and silicon-on-insulator planar waveguides

Abstract: We propose a compact and efficient grating coupler for vertical coupling between optical fibers and planar waveguides. A grating with a parallelogram shape is designed to be etched through the entire high-index waveguide core. The coupler is optimized using a microgenetic algorithm coupled with a two-dimensional finite-difference time-domain method. Simulations show that up to 75.8% coupling efficiency can be obtained between a single-mode fiber and a 240-nm-thick silicon-on-insulator planar waveguide.

Strain characterization in SOI and strained-Si on SGOI MOSFET channel using nano-beam electron diffraction (NBD)

Abstract: SOI MOSFETs are attractive device structures for high-performance CMOS because they offer the advantages of high-speed and low-power-dissipation operation. For next-generation devices, the combination of strained-Si channels and SOI substrates can be the optimum structure and, thus, we have developed strained-Si MOSFETs on thin relaxed SiGe-on-insulator (SGOI) substrates. However, the strain evaluation within the very thin and small SOI layers after device fabrication processes has not been investigated in detail yet because a strain evaluation method with lateral resolution of several nm, which can be applied directly to samples, has not been available. In this paper, we present a direct and two-dimensional strain evaluation with high spatial resolution using the nano-beam electron diffraction (NBD) method and results of direct strain measurements for conventional SOI and strained-Si on SGOI MOSFET channels.

Semiconductor device and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To remove adverse effects of current characteristics due to a parasitic MOS transistor formed at a boundary portion between an SOI layer and an LOCOS oxide film. SOLUTION: A semiconductor device of a SOI structure has a silicon substrate 1, an oxide film 2 for insulation formed on the silicon substrate 1, an SOI layer which consists of a silicon layer 3 formed on the oxide film 2 for insulation, an LOCOS oxide film 4 which is formed on the oxide film 2 for insulation and formed so as to be in contact with the SOI layer 3 for insulating the SOI layer 3, a gate insulating film 5 formed on the SOI layer 3, and a gate electrode 6 formed on the gate insulating film 5, wherein the cross sectional shape of a portion which is in contact with the LOCOS oxide film 4 of the SOI layer 3 is formed so as to cut into in the shape of approximately triangle, and the ratio of the perpendicular line in the thickness direction of the SOI layer 3 which constitutes the triangle and the boundary between the SOI layer 3 and the oxide film 2 for insulation is formed so as to be 4:1 or less. COPYRIGHT: (C)2006,JPO&NCIPI

Micro-gravity capacitive silicon-on-insulator accelerometers

Abstract: In this paper, the implementation and characterization of high-sensitivity in-plane capacitive micro-gravity silicon-on-insulator (SOI) accelerometers with the readout circuitry are presented The devices were implemented in 50 µm thick SOI substrates using a two-mask dry-release process The fabricated accelerometers were interfaced to a low-noise low-power reference-capacitor-less switched-capacitor circuit The integrated circuit (IC) was implemented in a 25 V 025 N-well CMOS process The measured capacitive sensitivity is 03 pF g−1, equivalent to a gain of 075 V g−1 The measured resolution is 11 µg Hz−1/2 at 2 Hz and 02 µg Hz−1/2 at 100 Hz (resolution bandwidth = 1 Hz) The interface IC operates from a single 25 V supply and measures a power consumption of 4 mW with a sampling clock of 100 kHz The core IC die size is 065 mm2

Demonstration of high Raman gain in a submicrometer-size silicon-on-insulator waveguide.

Abstract: We show high Raman gain in a silicon submicrometer-size planar waveguide. Using high-confinement structures and picosecond pump pulses, we show 3.1-dB net internal gain with 2.8-W peak pump power in a 7-mm-long waveguide. We also analyze experimentally and theoretically the effect of free-carrier absorption on the Raman gain.

Effective Schottky barrier lowering in silicon-on-insulator Schottky-barrier metal-oxide-semiconductor field-effect transistors using dopant segregation

Abstract: We present an investigation of the use of dopant segregation in Schottky-barrier metal-oxide-semiconductor field-effect transistors on silicon-on-insulator. Experimental results on devices with fully nickel silicided source and drain contacts show that arsenic segregation during silicidation leads to strongly improved device characteristics due to a strong conduction/valence band bending at the contact interface induced by a very thin, highly doped silicon layer formed during the silicidation. With simulations, we study the effect of varying silicon-on-insulator and gate oxide thicknesses on the performance of Schottky-barrier devices with dopant segregation. It is shown that due to the improved electrostatic gate control, a combination of both ultrathin silicon bodies and gate oxides with dopant segregation yields even further improved device characteristics greatly relaxing the need for low Schottky barrier materials in order to realize high-performance Schottky-barrier transistors.

Ultrahigh speed germanium-on-silicon-on-insulator photodetectors for 1.31 and 1.55μm operation

Abstract: We report the fabrication and the characterization of interdigited metal-germanium on silicon metal photodetectors (metal-semiconductor-metal or MSM) for operation at both optical telecommunication wavelengths: 1.31 and 1.55μm. Femtosecond impulse and frequency experiments have been carried out to characterize those MSM Ge photodetectors. For both wavelengths, the measured 3dB bandwidth under 2V bias are close to 10, 18, 20, and 35GHz for electrode spacings equal to 2000, 1000, 700, and 500nm, respectively.

SOI structure having a SiGe layer interposed between the silicon and the insulator

Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.

70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs)

Abstract: 70-nm I-MOS devices have been integrated with 70-nm TFETs for the first time by adopting a novel process method The integration of the I-MOS device with the TFET is meaningful in that it compensates for weak points of each device and implements both high-performance and low-power functionality on the same substrate Additionally, by using SOI substrate and modifying mask layout, ON/OFF current ratio of the I-MOS device is increased dramatically by a factor of more than 1000 compared with our previous works Finally, we have investigated the applicability of the I-MOS device to inverter and 6T-SRAM cell by measurement and mixed-mode simulation When applied to 6T-SRAM cell, CI-MOS case shows 226 % improvement in SNM without much penalty in cell area