Showing papers by "STMicroelectronics published in 2011"

Evolution of wireless sensor networks towards the Internet of Things: A survey

Abstract: Wireless Sensor Networks (WSNs) are playing more and more a key role in several application scenarios such as healthcare, agriculture, environment monitoring, and smart metering. Furthermore, WSNs are characterized by high heterogeneity because there are many different proprietary and non-proprietary solutions. This wide range of technologies has delayed new deployments and integration with existing sensor networks. The current trend, however, is to move away from proprietary and closed standards, to embrace IP-based sensor networks using the emerging standard 6LoWPAN/IPv6. This allows native connectivity between WSN and Internet, enabling smart objects to participate to the Internet of Things (IoT). Building an all-IP infrastructure from scratch, however, would be difficult because many different sensors and actuators technologies (both wired and wireless) have already been deployed over the years. After a review of the state of the art, this paper sketches a framework able to harmonize legacy and new installations, allowing migrating to an all-IP environment at a later stage. The Building Automation use case has been chosen to discuss potential benefits of the proposed framework.

Broadband terahertz imaging with highly sensitive silicon CMOS detectors

Abstract: This paper investigates terahertz detectors fabricated in a low-cost 130 nm silicon CMOS technology. We show that the detectors consisting of a nMOS field effect transistor as rectifying element and an integrated bow-tie coupling antenna achieve a record responsivity above 5 kV/W and a noise equivalent power below 10 pW/Hz(0.5) in the important atmospheric window around 300 GHz and at room temperature. We demonstrate furthermore that the same detectors are efficient for imaging in a very wide frequency range from ~0.27 THz up to 1.05 THz. These results pave the way towards high sensitivity focal plane arrays in silicon for terahertz imaging.

Duplexing the sponge: single-pass authenticated encryption and other applications

Abstract: This paper proposes a novel construction, called duplex, closely related to the sponge construction, that accepts message blocks to be hashed and---at no extra cost---provides digests on the input blocks received so far. It can be proven equivalent to a cascade of sponge functions and hence inherits its security against single-stage generic attacks. The main application proposed here is an authenticated encryption mode based on the duplex construction. This mode is efficient, namely, enciphering and authenticating together require only a single call to the underlying permutation per block, and is readily usable in, e.g., key wrapping. Furthermore, it is the first mode of this kind to be directly based on a permutation instead of a block cipher and to natively support intermediate tags. The duplex construction can be used to efficiently realize other modes, such as a reseedable pseudo-random bit sequence generators and a sponge variant that overwrites part of the state with the input block rather than to XOR it in.

A 160×128 single-photon image sensor with on-pixel 55ps 10b time-to-digital converter

Abstract: Image sensors capable of resolving the time-of-arrival (ToA) of individual photons with high resolution are needed in several applications, such as fluorescence lifetime imaging microscopy (FLIM), Forster resonance energy transfer (FRET), optical rangefinding, and positron emission tomography In FRET, for example, typical fluorescence lifetime is of the order of 100 to 300ps, thus deep-subnanosecond resolutions are needed in the instrument response function (IRF) This in turn requires new time-resolved image sensors with better time resolution, increased throughput, and lower costs Solid-state avalanche photodiodes operated in Geiger-mode, or single-photon avalanche diodes (SPADs), have existed for decades [1] but only recently have SPADs been integrated in CMOS However, as array sizes have grown, the readout bottleneck has also become evident, leading to hybrid designs or more integration and more parallelism on-chip [2,3] This trend has accelerated with the introduction of SPAD devices in deep-submicron CMOS, that have enabled the design of massively parallel arrays where the entire photon detection and ToA circuitry is integrated on-pixel [4,5]

Towards Miniaturization of a MEMS-Based Wearable Motion Capture System

Abstract: This paper presents a modular architecture to develop a wearable system for real-time human motion capture. The system is based on a network of smart inertial measurement units (IMUs) distributed on the human body. Each of these modules is provided with a 32-bit RISC microcontroller (MCU) and miniaturized MEMS sensors: three-axis accelerometer, three-axis gyroscopes, and three-axis magnetometer. The MCU collects measurements from the sensors and implement the sensor fusion algorithm, a quaternion-based extended Kalman filter to estimate the attitude and the gyroscope biases. The design of the proposed IMU, in order to overcome the problems of the commercial solution, aims to improve performance and to reduce size and weight. In this way, it can be easily embedded in a tracksuit for total body motion reconstruction with considerable enhancement of the wearability and comfort. Furthermore, the main achievements will be presented with a performance comparison between the proposed IMU and some commercial platforms.

Garbage collection in storage devices based on flash memories

Abstract: A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.

Multi- $V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Abstract: This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT ). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.

Advances, challenges and opportunities in 3D CMOS sequential integration

Abstract: 3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.

A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications

Abstract: This paper presents a fully integrated 60GHz transceiver module in a 65nm CMOS technology for wireless high-definition video streaming. The CMOS chip is compatible with the WirelessHD™ standard, covers the four channels and supports 16-QAM OFDM signals including the analog baseband. The ESD-protected die (9.3mm²) is flip-chipped atop a High Temperature Cofired Ceramic (HTCC) substrate, which receives also an external PA and the emission and reception glass-substrate antennas. The module occupies an area of only 13.5×8.5mm². It consumes 454mW in receiver mode and 1.357W in transmitter mode (357mW for the transmitter and 1W for the PA).

Characteristics of the Electrical Percolation in Carbon Nanotubes/Polymer Nanocomposites

Abstract: We study the onset of electrical percolation in multiwalled carbon nanotubes (MWNTs)/epoxy nanocomposites. Experiments show a threshold value of 3.2 wt % of MWNTs for percolation to occur. Simulations based on two varied approaches are carried out to evaluate the conductivity characteristics resulting from increasing MWNT content. Simple Monte Carlo simulations in which MWNTs are modeled as either 1D sticks or 2D narrow rectangles dispersed in a 2D simulation volume are shown to yield a percolation threshold in close agreement with experiments. We find that a higher degree of anisotropy in the orientation of nanotubes or of the waviness leads to an increase in the percolation threshold. A more insightful approach encompassing the quantum tunneling effect is also undertaken using the tight-binding simulations. Consideration of the tunneling effect is found to be particularly important when the nanotube aspect ratio is small, the case in which simpler Monte Carlo simulations overestimate the percolation thr...

Method for manufacturing a polycrystalline dielectric layer

Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.

Circuit architecture on an organic base and related manufacturing method

Abstract: A method comprises providing a bottom electrode, depositing, on the bottom electrode, an active material comprising a first structural portion having an absorption peak at a UV wavelength, wherein such first structural portion is photo-activatable at such wavelength and which is constituted by monomers or oligomers that, when irradiated at said wavelength, undergo a photo-polymerization and/or photo-cross-linking reaction, or constituted by a polymer that at a UV wavelength undergoes a photo-degradation reaction, and a second electrically active or activatable structural portion which is substantially transparent to such predetermined UV wavelength; exposing a portion of the active material, through a photomask, to UV radiation having such UV wavelength, with photo-activation of the exposed portion of such film; selectively removing either the exposed photo-activated portion or the non-exposed portion, with exposure of a respective portion of the bottom electrode; depositing a head electrode.

Video-rate fluorescence lifetime imaging camera with CMOS single-photon avalanche diode arrays and high-speed imaging algorithm

Abstract: A high-speed and hardware-only algorithm using a center of mass method has been proposed for single-detector fluorescence lifetime sensing applications. This algorithm is now implemented on a field programmable gate array to provide fast lifetime estimates from a 32 × 32 low dark count 0.13 ?m complementary metaloxide-semiconductor single-photon avalanche diode (SPAD) plus time-to-digital converter array. A simple look-up table is included to enhance the lifetime resolvability range and photon economics, making it comparable to the commonly used least-square method and maximum likelihood estimation based software. To demonstrate its performance, a widefield microscope was adapted to accommodate the SPAD array and image different test samples. Fluorescence lifetime imaging microscopy on fluorescent beads in Rhodamine 6G at a frame rate of 50 fps is also shown.

Embedded wafer level package for 3D and package-on-package applications, and method of manufacture

Abstract: An eWLB package for 3D and PoP applications includes a redistribution layer on a support wafer. A semiconductor die is coupled to the redistribution layer, and solder balls are also positioned on the redistribution layer. The die and solder balls are encapsulated in a molding compound layer, which is planarized to expose top portions of the solder balls. A second redistribution layer is formed on the planarized surface of the molding compound layer. A ball grid array can be positioned on the second redistribution layer to couple the semiconductor package to a circuit board, or additional semiconductor dies can be added, each in a respective molding compound layer. The support wafer can act as an interposer, in which case it is processed to form TSVs in electrical contact with the first redistribution layer, and a redistribution layer is formed on the opposite side of the support substrate, as well.

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology

Abstract: State-of-the-art System-on-Chip (SoC) consists of hundreds of processing elements, while trends in design of the next generation of SoC point to integration of thousand of processing elements, requiring high performance interconnect for high throughput communications. Optical on-chip interconnects are currently considered as one of the most promising paradigms for the design of such next generation Multi-Processors System on Chip (MPSoC). They enable significantly increased bandwidth, increased immunity to electromagnetic noise, decreased latency, and decreased power. Therefore, defining new architectures taking advantage of optical interconnects represents today a key issue for MPSoC designers. Moreover, new design methodologies, considering the design constraints specific to these architectures are mandatory. In this paper, we present a contention-free new architecture based on optical network on chip, called Optical Ring Network-on-Chip (ORNoC). We also show that our network scales well with both large 2D and 3D architectures. For the efficient design, we propose automatic wavelength-/waveguide assignment and demonstrate that the proposed architecture is capable of connecting 1296 nodes with only 102 waveguides and 64 wavelengths per waveguide.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Abstract: Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

Towards THz SiGe HBTs

Abstract: This paper summarizes the technological developments carried out on SiGe HBTs in the frame of the European project DOTFIVE. The architectures of the different partners and their performances are presented and discussed showing that the project objectives have been met.

Fundamental aspects of HfO 2 -based high-k metal gate stack reliability and implications on t inv -scaling

Abstract: Experimental reliability trends indicate that t inv -scaling with HKMG stacks remains challenging because NBTI, PBTI and TDDB reliability margins rapidly decrease with decreasing t inv values and increasing gate leakage current. A case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO 2 dual dielectric. Therefore, fundamental reliability limitations appear to increasingly impact HKMG stack scaling.

Apparatus for power wireless transfer between two devices and simultaneous data transfer

Abstract: A system for the wireless transfer of power includes a first device connected to a power supply source and provided with a first resonant circuit at a first frequency, a second device comprising at least one battery, provided with a second resonant circuit at said first frequency, arranged at a distance smaller than the wavelength associated with said first frequency and not provided with wires for the electrical connection with said first device. The first device is adapted to transfer a first signal representing the power to be sent to the second device for charging said at least one battery and comprises means adapted to modulate the frequency of said first signal for transferring data from the first device to the second device simultaneously with the power transfer. The second device comprises means adapted to demodulate the received signal, corresponding to the first signal sent from the first device, to obtain the transmitted data.

A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology

Abstract: A 4 Mb embedded phase change memory macro has been developed in a 90 nm 6-ML CMOS technology. The storage element has been integrated using 3 additional masks with respect to process baseline. The cell selector is implemented by a standard LV nMOS device, achieving a cell size of 0.29 μm2. A dual-voltage row decoder and a double-path column decoder are introduced, enabling a completely low voltage read operation. A 20b-parallelism write scheme is embedded in the digital controller in order to maximize throughput. In alternative, a power-saving low-parallelism write algorithm can be employed. The macro features a 1.2 V 12 ns read access time and a write throughput of 1 MB/s. Set and reset current distributions showing a good read window are presented and robust reliability results are demonstrated.

Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques

Abstract: An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains Scan structures like the OCCs, scan chain, etc, may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer

Varifocal liquid lenses with integrated actuator, high focusing power and low operating voltage fabricated on 200 mm wafers

Abstract: We developed an innovative type of varifocal liquid lens actuated by electrostatic parallel plates. The 3 mm diameter lens is made of a polymer membrane that encapsulates a high permittivity liquid in a cavity on top of a glass wafer. Annular electrodes situated below the membrane and on the glass wafer form the electrostatic parallel plates actuator. By applying a voltage between the electrodes, the electrostatic actuation generated reduces the gap and pushes the liquid towards the center of the lens changing the curvature of the membrane. Compared to previous liquid lenses, very compact devices (≤6 mm × 6 mm × 0.7 mm) working at a reduced supply voltage ( −1 at 22 V RMS that can be further improved. The lenses were fabricated on 200 mm wafers using standard microelectronics processes that make our solution a promising small outline, low voltage and low cost candidate for auto-focus devices in camera phones.

A low-power 3-axis digital-output MEMS gyroscope with single drive and multiplexed angular rate readout

Abstract: Motivated by the increasing demand of integrated inertial-sensing solutions for motion processing and dead-reckoning navigation in handheld devices and low-cost GPS navigators, this paper reports the details of a 3-axis silicon MEMS vibratory gyroscope that fulfills the pressing market requirements for low power consumption, small size and low cost. Thanks to a compact mechanical design that combines a triple tuning-fork structure within a single vibrating element, our solution achieves satisfactory performance in terms of thermal stability, cross-axis error, and acoustic noise immunity by using a small die size. Furthermore, the presence of a single primary vibration mode for the excitation of the 3 tuning-forks, together with the possibility of sensing the pickoff modes in a multiplexing fashion, allows to design a small-area, low-power ASIC.

Color filters including infrared cut-off integrated on CMOS image sensor.

Abstract: A color image was taken with a CMOS image sensor without any infrared cut-off filter, using red, green and blue metal/dielectric filters arranged in Bayer pattern with 1.75µm pixel pitch. The three colors were obtained by a thickness variation of only two layers in the 7-layer stack, with a technological process including four photolithography levels. The thickness of the filter stack was only half of the traditional color resists, potentially enabling a reduction of optical crosstalk for smaller pixels. Both color errors and signal to noise ratio derived from optimized spectral responses are expected to be similar to color resists associated with infrared filter.

A 128×96 pixel event-driven phase-domain ΔΣ-based fully digital 3D camera in 0.13μm CMOS imaging technology

Abstract: Low-cost 3D image capture devices are enabling new applications in the gaming, robotics, automotive and surveillance industries. A number of approaches are competing for a share of these markets. Stereoscopic cameras employ intensive image processing to interpret distance from the correlation of two separate image streams [1], structured light systems analyse the deformation of patterned light projected over the scene, while time-of-flight (TOF) cameras require custom frequency-modulated image sensors and optical sources to measure the phase or return time of reflected light pulses. As rapid progress is made on compact, high-frequency NIR LEDs, much research is being devoted to improvements in the size, sensitivity and resolution of TOF image sensors. Analog pixel approaches provide compact pixel implementations but accuracy is limited by noise sources and nonlinearities of the analog electronics [2]. Single Photon Avalanche Diodes (SPADs) circumvent these issues and enable fully digital distance computation down to millimetric accuracy [3] by either direct or indirect demodulation schemes.

Multiple touch location in a three dimensional touch screen sensor

Abstract: A touch screen capable of correctly identifying multiple touches employs multiple active line arrays oriented to provide multi-dimensional data. Three arrays of capacitance based active lines are each distinctly oriented to form a plurality of intersections. A first and second array are generally oriented perpendicularly while a third array is oriented to bisect the resulting matrix such that the active lines of the third array also intersect the existing vertices. As a result of a touch each active line array identifies the location of the touch from three distinct directions. Ambiguity from dual touch scenarios existing in dual array systems is removed by providing an additional reference.

Carbon-doped GeTe: A promising material for Phase-Change Memories

Abstract: This paper investigates Carbon-doped GeTe (GeTeC) as novel material for Phase-Change Memories (PCM). In the first part of the manuscript, a study of GeTeC blanket layers is presented. Focus is on GeTeC amorphous phase stability, which has been studied by means of optical reflectivity and electrical resistivity measurements, and on GeTeC structure and composition, analyzed by XRD and Raman spectroscopy. Then, electrical characterization of GeTeC-based PCM devices is reported: resistance drift, data retention performances, RESET current and power, and SET time have been investigated. Very good data retention properties and reduction of RESET current make GeTeC suitable for both embedded and stand-alone PCM applications, thus suggesting GeTeC as promising candidate to address some of the major issues of today’s PCM technology.

Resistance increase due to electromigration induced depletion under TSV

Abstract: This paper focuses on the EM induced voiding in a line ended by a TSV, and proposes an analytical model based on the link between the monitored electrical resistance increase and the matter depletion flow.