Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
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TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
Citations
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Journal ArticleDOI
Universality in electron-modulated-acoustic-phonon interactions in a free-standing semiconductor nanowire
TL;DR: It is shown that the form factor is a key quantity in discussing the impact of acoustic phonons on electron transport, and it has a universality independent of the wire material and radius.
Journal ArticleDOI
Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature
Yi Han,Jingxuan Sun,B. Richstein,Frederic Allibert,Ionut Radu,Jin Hee Bae,Detlev Grützmacher,Joachim Knoch,Qing-T. Zhao +8 more
TL;DR: Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm were fabricated and characterized from room temperature (RT) down to 5.5 K as discussed by the authors .
Journal ArticleDOI
Junctionless CMOS Transistors with Independent Double Gates
TL;DR: In this paper, a junction-less FiNFET like transistor is proposed, where the gate definition in this device is lithography independent and the transistor is fabricated using NMOS and PMOS.
Proceedings ArticleDOI
Structure Effects in the gate-all-around Silicon Nanowire MOSFETs
TL;DR: In this paper, the authors theoretically examined the structure effects (cross-section shape, channel orientation and the size of nanowires) of the gate-all-around silicon nanowire metal-oxide-semiconductor field effect transistors (MOSFETs) on their ultimate performance.
Proceedings ArticleDOI
Full-band simulation of p-type ultra-scaled silicon nanowire transistors
Aron Szabo,Mathieu Luisier +1 more
TL;DR: A computationally efficient full-band approach to simulate the current characteristics of p-type ultra-scaled, circular, gate-all-around nanowire field-effect transistors (FETs) based on an extension of the semiclassical top-of-the-barrier model where tunneling is accounted for through the Wentzel-Kramers-Brillouin approximation and Poisson equation is reduced to a one-dimensional problem.
References
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TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
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TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
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