Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
Citations
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Journal ArticleDOI
Carbon Nanotubes for High-Performance Electronics—Progress and Prospect
TL;DR: By understanding the unique capabilities of carbon nanotubes and using them in unconventional designs, novel nanoelectronic applications may become feasible and much better control of materials quality must be obtained, and new fabrication processes must be developed before such applications can be realized.
Journal ArticleDOI
Bandstructure Effects in Silicon Nanowire Electron Transport
TL;DR: In this article, a 10-band sp3d5s* semi-empirical atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the dispersion calculation.
Journal ArticleDOI
Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
Navab Singh,K.D. Buddharaju,Sanjeev Kumar Manhas,Ajay Agarwal,S.C. Rustagi,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +7 more
TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Journal ArticleDOI
Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits.
TL;DR: The proposed silicon nanotube field effect transistor offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.
Journal ArticleDOI
Scaling of Nanowire Transistors
TL;DR: In this article, the scaling of nanowire transistors to 10-nm gate lengths and below is considered and compared with the published experimental data of nan-wire transistors, and the performance limit of a nan-ire transistor is assessed by applying a ballistic current model.
References
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Surface Charge Density of Unpassivated and Passivated Metal-Catalyzed Silicon Nanowires
TL;DR: In this article, the surface-charge density of a nanowire covered with native oxide is about 2 X 10 12 cm -2 ; the density appears to decrease by a factor of two to four when the native oxide was replaced by a high-quality thermally grown oxide, with further improvement possible.
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Photoinduced bending and unbending behavior of liquid-crystalline gels and elastomers
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Journal ArticleDOI
Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation
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Journal ArticleDOI
Low-temperature electron mobility in Trigate SOI MOSFETs
Jean-Pierre Colinge,Aidan J. Quinn,Liam Floyd,Gareth Redmond,John Alderman,Weize Xiong,C.R. Cleavelin,T. Schulz,Klaus Schruefer,G. Knoblinger,P. Patruno +10 more
TL;DR: In this paper, one-dimensional subband formation was found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics.
Journal ArticleDOI
On the accuracy of channel length characterization of LDD MOSFET's
TL;DR: In this article, a comprehensive investigation into the various mechanisms that limit the accuracy of channel length extraction techniques for lightly doped drain (LDD) MOSFET's is presented.