Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
Citations
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Journal ArticleDOI
Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel
Hung-Bin Chen,Chun-Yen Chang,Nan-Heng Lu,Jia-Jiun Wu,Ming-Hung Han,Ya-Chi Cheng,Yung-Chun Wu +6 more
TL;DR: In this paper, the junctionless gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm) were demonstrated for the first time.
Journal ArticleDOI
Ge-Rich (70%) SiGe Nanowire MOSFET Fabricated Using Pattern-Dependent Ge-Condensation Technique
Y. Jiang,Navab Singh,Tsung-Yang Liow,W.Y. Loh,Subramanian Balakumar,Keat Mun Hoe,C.H. Tung,Vladimir Bliznetsov,S.C. Rustagi,Guo-Qiang Lo,D. S. H. Chan,Dim-Lee Kwong +11 more
TL;DR: In this article, a top-down approach of forming SiGe-nanowire (SGNW) MOSFET, with Ge concentration modulated along the source/drain (Si0.7Ge0.3) to channel (Si 0.3Ge 0.7) regions, is presented.
Journal ArticleDOI
Design space for low sensitivity to size variations in [110] PMOS nanowire devices: the implications of anisotropy in the quantization mass.
TL;DR: The considerations of the full band model here show that ON-current doubling can be observed in the ON-state at the onset of volume inversion to surface inversion transport caused by structural side size variations.
Journal ArticleDOI
High-Performance Silicon Nanowire Gate-All-Around nMOSFETs Fabricated on Bulk Substrate Using CMOS-Compatible Process
TL;DR: In this article, a self-aligned CMOS compatible method for the fabrication of gate-all-around silicon nanowire MOSFETs (GAA SNWFETs) on bulk substrate has been proposed.
Journal ArticleDOI
Impact of Gate Electrodes on $\hbox{1}/f$ Noise of Gate-All-Around Silicon Nanowire Transistors
Chengqing Wei,Yu Jiang,Yong-Zhong Xiong,Xing Zhou,Navab Singh,S.C. Rustagi,Guo-Qiang Lo,Dim-Lee Kwong +7 more
TL;DR: In this article, the low-frequency (1/f) noise of gate-all-around silicon transistors (SNWTs) with different gate electrodes (poly-Si gate, doped fully silicided (FUSI) gate, and undoped FUSI gate) is studied in the strong-inversion linear region.
References
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Journal ArticleDOI
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TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Journal ArticleDOI
Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires*
Yu Huang,Charles M. Lieber +1 more
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