Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
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TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
Citations
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Journal ArticleDOI
Effect of Oxidation-Induced Tensile Strain on Gate-All-Around Silicon-Nanowire-Based Single-Electron Transistor Fabricated Using Deep-UV Lithography
Yongshun Sun,Rusli,Navab Singh +2 more
TL;DR: In this paper, the electrical characteristics of gate-all-around silicon nanowires (SiNWs) based single-electron transistors (SETs) operating at room temperature were investigated.
Proceedings ArticleDOI
A comprehensive atomistic analysis of bandstructure velocities in si nanowires
TL;DR: In this article, a 20 band sp3 d5 s∗ spin-orbit-coupled, semi-empirical, atomistic tight-binding (TB) model is used with a semi-classical, ballistic transport model, to theoretically examine the bandstructure carrier velocity under non-degenerate conditions in silicon nanowire (NW) transistors.
Journal ArticleDOI
Moderate bending strain induced semiconductor to metal transition in Si nanowires
TL;DR: In this paper, the influence of bending on silicon nanowires of 1 nm to 4.3 nm diameter was investigated using molecular dynamics and quantum transport simulations, and the effect of bending strain and nanowire diameter on electronic transport and the transmission energy gap was analyzed.
Band-to-Band Tunneling Transistors: Scalability and Circuit Performance
TL;DR: In this article, a TCAD analysis tool with dynamic nonlocal tunneling path determination is calibrated to experimental data, and an optimal source design for TFETs is found where a moderate doping concentration (~1019 cm-3) is found to be preferable to the higher doping concentrations more commonly used.
References
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High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Journal ArticleDOI
Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
C.P. Auth,James D. Plummer +1 more
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Journal ArticleDOI
Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires*
Yu Huang,Charles M. Lieber +1 more
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.