Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
Citations
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Journal ArticleDOI
Simulation of Quantum Current Oscillations in Trigate SOI MOSFETs
Nima Dehdashti Akhavan,Aryan Afzalian,Chi-Woo Lee,Ran Yan,Isabelle Ferain,Pedram Razavi,Giorgos Fagas,Jean-Pierre Colinge +7 more
TL;DR: In this paper, the formation of 1-D subbands in trigate silicon-on-insulator (SOI) nanowire field effect transistors using 3-D numerical simulations was studied in detail.
Journal ArticleDOI
TCAD study on gate-all-around cylindrical (GAAC) transistor for CMOS scaling to the end of the roadmap
TL;DR: TCAD study on gate-all-around cylindrical (GAAC) transistor for sub-10-nm scaling is reported and the GAAC transistor device physics, TCAD simulation, and proposed fabrication procedure have been discussed.
Carbon Nanotubes for High-Performance Electronics-Progress and Prospect : The prospect, for nanotube field effect transistors that can compete with silicon technology, is extremely promising but critical tasks still lie ahead
TL;DR: Carbon nanotubes offer intrinsic advantages for high-performance logic device applications as discussed by the authors, while the intrinsic transport properties of the nanotube ensure at the same time high on-currents.
Journal ArticleDOI
Characterization and Modeling of Subfemtofarad Nanowire Capacitance Using the CBCM Technique
Hui Zhao,Raseong Kim,Abhijeet Paul,Mathieu Luisier,Gerhard Klimeck,Fa-Jun Ma,S.C. Rustagi,Ganesh S. Samudra,Navab Singh,Guo-Qiang Lo,Dim-Lee Kwong +10 more
TL;DR: In this article, a charge-based capacitance measurement (CBCM) technique was used to measure the gate capacitance of a single-channel nanowire transistor and validated by 3-D electrostatic computations for parasitic estimation and 2-D self-consistent sp3s* d5 tight-binding computations.
Journal ArticleDOI
Analytical Threshold Voltage Modeling of Surrounding Gate Silicon Nanowire Transistors with Different Geometries
TL;DR: In this article, the authors proposed new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries, which explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET.
References
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TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Journal ArticleDOI
Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
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TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Journal ArticleDOI
Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires*
Yu Huang,Charles M. Lieber +1 more
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