Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
Citations
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Dissertation
Intégration de transistor mono-électronique et transistor à atome unique sur CMOS
TL;DR: In this article, the authors propose a solution for the scaling of MOSFET by reducing the dimensions of the longueur de canal of the transistors in order to reduce the number of transistors required.
Structure Effects inthegate-all-around Silicon Nanowire MOSFETs
TL;DR: In this paper, the authors theoretically examined the structure of nanowires and showed that the triangular nanowire MOSFETs capacitance was the best among all the different types of silicon-based transistors.
Proceedings ArticleDOI
Hot carrier degradation in nanowire (NW) FinFETs
Tapas K. Maiti,Milan Kumar Bera,S. S. Mahato,P. Chakraborty,Chandreswar Mahata,M. Sengupta,A. Chakraborty,C. K. Maiti +7 more
TL;DR: In this paper, a quasi-two dimensional (quasi-2D) physics-based screening Coulomb scattering mobility model has been developed and implemented in Synopsys Sentaurus Device simulator.
Proceedings ArticleDOI
Simulation of correlated line-edge roughness in multi-gate devices
TL;DR: In this paper, the impacts of correlated line-edge roughness (LER) on the performance of Si channel fabrication were investigated. And the results showed that the device Vth distribution is strongly dependent on the cross-correlation, and can exhibit non-Gaussian distribution.
Journal ArticleDOI
Characterization of Fully Silicided Source/Drain SOI UTBB nMOSFETs at Cryogenic Temperatures
Yi Han,Feng Xi,Frederic Allibert,Ionut Radu,Slawomir Prucnal,Jin Hee Bae,Susanne Hoffmann-Eifert,Joachim Knoch,Detlev Grützmacher,Qing-T. Zhao +9 more
TL;DR: In this paper , the impact of the back-gate (V back ) on the device performance is systematically investigated, and the results demonstrate that V back is essential to tune the threshold voltage V th.
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