Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
- pp 1-4
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TLDR
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.Abstract:
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as wellread more
Citations
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Proceedings ArticleDOI
Dependence of Injection Velocity and Capacitance of Si Nanowires on Diameter, Orientation, and Gate Bias: An Atomistic Tight-Binding Study
TL;DR: In this article, a simulation study of Si nanowire (NW) transistor devices for logic applications using an atomistic tight-binding (TB) model for the electronic structure calculation, self consistently coupled to a two-dimensional Poisson solver for the solution of the electrostatics.
DissertationDOI
Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors
Journal ArticleDOI
Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor
TL;DR: In this article, the size dependence of the time-dependent dielectric breakdown in a tri-gate nanowire transistor (NW Tr) was investigated and it was found that TDDB reliability is degraded in NW Tr. as compared with that in a planar transistor owing to the locally enhanced electric field at the NW corner.
Journal ArticleDOI
Capacitance Oscillations in Cylindrical Nanowire Gate-All-Around MOS Devices at Low Temperatures
S.K. Chin,V. Ligatchev +1 more
TL;DR: In this article, the effects of strong transverse confinement on cylindrical nanowire (NW) gate-all-around MOS were studied using a Schrodinger-Poisson simulator with full-quantum treatment.
Journal Article
Impact of Process Variations on the Vertical Silicon Nanowire Tunneling FET (TFET)
TL;DR: In this article, the authors present device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET) and show that the gate length needs to be more than the nano-width to prevent short channel effects.
References
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Journal ArticleDOI
Semiconductor nanowires and nanotubes
TL;DR: In this article, a review highlights the recent advances in the field, using work from this laboratory for illustration, and the understanding of general nanocrystal growth mechanisms serves as the foundation for the rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks.
Journal ArticleDOI
High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
Navab Singh,Ajay Agarwal,Lakshmi Kanta Bera,Tsung-Yang Liow,R. Yang,S.C. Rustagi,C.H. Tung,Rakesh Kumar,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +10 more
TL;DR: In this article, gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator with 5-nm-diameter laterally formed Si nanowire channel were demonstrated.
Journal ArticleDOI
Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
C.P. Auth,James D. Plummer +1 more
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Journal ArticleDOI
Multiple-gate SOI MOSFETs: device design guidelines
TL;DR: In this paper, the authors describe computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices.
Journal ArticleDOI
Integrated nanoscale electronics and optoelectronics: Exploring nanoscale science and technology through semiconductor nanowires*
Yu Huang,Charles M. Lieber +1 more
TL;DR: In this paper, a general approach for the synthesis of a broad range of semiconductor nanowires (NWs) with precisely controlled chemical composition, physical dimension, and electronic, optical properties using a metal cluster-catalyzed vapor-liquid-solid growth mechanism was introduced.