Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Semiconductor package with improved redistribution layer design and fabricating method thereof

Abstract: A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled to a solder bump via under bump metal layers. A second RDL is formed in a same plane of the semiconductor die as the first RDL and is electrically isolated from the first RDL. A first end of the second RDL may be coupled to a bond pad and the second RDL may pass underneath, but be electrically isolated from, the solder bump. A passivation layer may be formed on the first and second RDLs exposing the second end of the first RDL. The under bump metal layers may be formed on the second end of the first RDL exposed by the passivation layer.

Wafer-level chip-scale package

Abstract: A wafer-level chip-scale package includes a semiconductor die having planar top and bottom surfaces and a plurality of metal pads formed at the top surface in an area array. A first protective layer is formed on the top surface of the semiconductor die, the first protective layer having a plurality of first apertures for allowing the metal pads to be opened upward. A second protective layer is formed on a surface of the first protective layer, the second protective layer having a plurality of second apertures which are larger than and overly corresponding first apertures of the first protective layer so that regions of the metal pads and the first protective layer are exposed to the outside of the semiconductor die. Solder balls are fused to each metal pad, which are opened to the outside through the first apertures of the first protective layer and the second apertures of the second protective layer.

Straight conductor blind via capture pad structure and fabrication method

Abstract: A capture pad structure includes a first dielectric layer. A trace is embedded within the first dielectric layer. A capture pad is also embedded within the first dielectric layer, the capture pad being an end portion of the trace. A blind via aperture extends partially through the first dielectric layer from a principal surface of the first dielectric layer to the capture pad. By forming the capture pad as the end portion of the trace, formation of the capture pad requires no change in direction or complex motion of the laser.

Wire fence fingerprint sensor package and fabrication method

Abstract: A wire fence fingerprint sensor package includes a substrate, a fingerprint sensor mounted to the substrate, and a wire fence mounted to the substrate adjacent the fingerprint sensor. During use, the wire fence is electrically connected to a reference voltage source, e.g., ground. Thus, the wire fence discharges electrostatic discharge (ESD) from a finger contacting the wire fence fingerprint sensor package. The wire fence is formed of low cost wire loops that are fabricated, for example, using a standard and inexpensive wire bonding apparatus. Accordingly, the wire fence fingerprint sensor package is fabricated at a minimal cost.

Electromigration reliability and current carrying capacity of various WLCSP interconnect structures

Abstract: Wafer Level Chip Scale Packages (WLCSPs) are increasingly being used in Power Management IC (PMIC) applications. Since these packages are typically of small size and low I/O count, the current per bump can be very high for these applications. Therefore, it is important to characterize the electromigration (EM) behavior of WLCSP interconnects to estimate their current carrying capacity. This paper provides an EM performance comparison of four (4) different WLCSP interconnects tested under the same condition. The configurations included: i) Ti/Cu/2.0 μm Ni UBM on 4μm Cu RDL, ii) Ti/Cu/8.6μm Cu UBM on 4μm Cu RDL, iii) Bump-on-trace with 9μm thick Cu RDL, and iv) Bump-on-trace with 14μm thick Cu RDL. A specially designed test vehicle with multiple EM test structures was used for this purpose. The packages were mounted on printed wiring boards (PWB) with either Cu/OSP or NiAu pad surface finish. These assemblies were then tested in a dedicated EM test system using 1.0Amp/161°C as the test condition. More than 4000 hours of testing have been completed so far. Clear differences between these WLCSP interconnects were observed in terms of EM performance. Samples were also removed at different times throughout the test so that detailed SEM analyses could be performed to understand and quantify the failure mode and progression of EM damage for each configuration. The EM performance is found to be significantly better for structures with a 2.0μm Ni UBM layer and the bump-on-trace structure with 14μm thick RDL with no failures so far. However, units with either 8.6μm thick Cu UBM structure or 9μm thick RDL bump-on-trace structure have resulted in a number of failures and at least 2X lower reliability compared to the other two structures. Further, PWB surface finish has a significant effect on EM performance with Cu/OSP performing better than NiAu finish.