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Institution

Amkor Technology

CompanyTempe, Arizona, United States
About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..


Papers
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Patent
09 Dec 2008
TL;DR: In this article, a semiconductor device has a first substrate having a plurality of metal traces and an RF shield is formed on the first substrate to minimize Electro Magnetic Interference (EMI) radiation and Radio Frequency (RF) radiation to the at least one electronic component on the second substrate.
Abstract: A semiconductor device has a first substrate having a plurality of metal traces. At least one electronic component is electrically attached to a first surface of the first substrate. A second substrate has a plurality of metal traces and attached to the first substrate. At least one electronic component is electrically attached to a first surface of the second substrate. An RF shield is formed on the first substrate to minimizing Electro-Magnetic Interference (EMI) radiation and Radio Frequency (RF) radiation to the at least one electronic component on the first substrate to form an RF shield. A mold compound is used for encapsulating the semiconductor device.

19 citations

Patent
Jon T. Woodyard1
27 Jun 2005
TL;DR: In this article, an internal package is mounted to the mother board in a single operation thus minimizing labor and the associated manufacturing cost, and the package is tested and verified to be non-defective prior to mounting to a mother board.
Abstract: A package includes an internal package stacked upon a primary die. The package includes interconnection balls to allow the package to be electrically and physically connected to a mother board. The package is mounted to the mother board in a single operation thus minimizing labor and the associated manufacturing cost. Further, the package is tested and verified to be non-defective prior to mounting to the mother board.

19 citations

Journal ArticleDOI
Dong Gun Kam1, Joungho Kim1, Jiheon Yu2, Ho Choi2, Kicheol Bae2, Choonheung Lee2 
TL;DR: This article addresses problems with wire bonding in high-frequency SiP packages and proposes design methodologies to reduce these discontinuities.
Abstract: System-in-package provides highly integrated packaging with high-speed performance Many SiP packages contain low-cost 3D stacked chips interconnected by fine wire bonds In a high-frequency spectrum, these wire bonds can cause discontinuities causing signal degradation This article addresses problems with wire bonding in high-frequency SiP packages and proposes design methodologies to reduce these discontinuities

19 citations

Patent
26 Sep 2003
TL;DR: In this paper, an electrical substrate useful for semiconductor packages is disclosed, which includes a core insulative layer with circuit patterns that are stepped in their heights from the first surface.
Abstract: An electrical substrate useful for semiconductor packages is disclosed. The electrical substrate includes a core insulative layer. A first surface of the insulative layer has circuit patterns thereon. Some of the circuit patterns are stepped in their heights from the first surface, in that a first subportion of the circuit pattern, including a ball land, extends further from the first surface than a second subportion of the same circuit pattern, and also extends further from the first surface than a ball land of other circuit patterns. Accordingly, solder balls fused to the ball lands of the stepped circuit patterns extend further from the first surface than same-size solder balls fused to the ball lands of the non-stepped circuit patterns, thereby circumventing electrical connectivity problems that may arise from warpage of the electrical substrate.

19 citations

Proceedings ArticleDOI
27 May 2008
TL;DR: In this paper, the effect of joint size and pad metallization on solder behavior was evaluated and it was found that larger joints were more prone to brittle interface failure than smaller joints.
Abstract: Metallurgical analysis, mechanical testing, and finite element analysis were conducted to understand the effect of joint size and pad metallization on solder behavior. A wide range of design and material variables was evaluated. The pad metallization affected both the intermetallic compounds at the joint interfaces and those dispersed in the bulk solder. NiAu pad metallization resulted in more creep resistant joints than Cu. These effects were more pronounced at lower test temperatures. Solder joint creep resistance increased with joint size. Larger joints were also more prone to brittle interface failure than smaller joints. This was true in both package level tests and board level tests. Finite element analysis indicated that the predicted fatigue life in cyclic drop or temperature cycle testing can be significantly affected by the test vehicle used to generate data for constitutive constants. More creep resistant behavior resulted in lower strain and work for both temperature cycle and drop test conditions. When comparing strain vs. work as a damage indicator, it is seen that work is less sensitive to variations in the constitutive constants.

19 citations


Authors

Showing all 1070 results

NameH-indexPapersCitations
Thomas P. Glenn481306676
Dong-Hoon Lee4876223162
Joungho Kim405797365
Steven Webster34833322
Young Bae Park332164325
Roy Dale Hollaway28532324
Ronald Patrick Huemoeller26912385
Robert Francis Darveaux23701881
MinJae Lee23993083
Il Kwon Shim21411403
Vincent DiCaprio20271973
Sukianto Rusli19441308
Glenn A. Rinne1934898
Ahmer Syed18551192
David Jon Hiner18541173
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20221
202112
202022
201922
201832
201728