Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages

Abstract: Chip-scale semiconductor packages of the fan-out type and methods of manufacturing such packages are disclosed. In one package embodiment within the invention, the package substrate is stiff enough to effectively carry an increased number of solder balls on an exterior area outside the edge of a semiconductor chip, in addition to the area above the chip. In another package embodiment, a molded support is mounted to the lower surface of the exterior area. The methods of the present invention include making a plurality of packages on a substrate. Prior to sawing a wafer to obtain chips for the assembly method, the wafer is inspected so as to discriminate between good chips and the defective chips. Only good chips are mounted to a wafer-shaped or strip-shaped substrate.

Integrated circuit substrate having laser-embedded conductive patterns and method therefor

Abstract: An integrated circuit substrate having laser-embedded conductive patterns provides a high-density mounting and interconnect structure for integrated circuits. Conductive patterns within channels on the substrate provide interconnects that are isolated by the channel sides. A dielectric material is injection-molded or laminated over a metal layer that is punched or etched. The metal layer can provide one or more power planes within the substrate. A laser is used to ablate channels on the surfaces of the outer dielectric layer for the conductive patterns. The conductive patterns are electroplated or paste screen-printed and an etchant-resistive material is applied. Finally, a plating material can be added to exposed surfaces of the conductive patterns. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.

Ball grid array semiconductor package using a metal carrier ring as a heat spreader

Abstract: A ball grid array semiconductor package includes a semiconductor chip mounted to the top side of a printed circuit board (PCB), having a copper circuit pattern at a position outside a chip mounting zone. A plurality of bond wires electrically connect the chip to the copper circuit pattern. A rectangular ring-shaped metal heat spreader is attached to the PCB surrounding the chip, with the outer periphery of the ring substantially coextensive with the outer periphery of the PCB. A molding compound is provided in a zone inside the heat spreader thus protecting the chip and wires from atmosphere, while the molding compound extends to a heat spreader portion, leaving other portions of the heat spreader exposed to atmosphere. A plurality of solder balls are included on the bottom side of the PCB and are used as signal input and output terminals of the package. The BGA package easily dissipates heat during the operation of the package, improving the operational reliability of the package. A plurality of grooves may be formed on the heat spreader, to improve the integrating force between the molding compound and the heat spreader and to protect the chip from moisture.

Study of interconnection process for fine pitch flip chip

Abstract: Today, flip chip technology is a main stream of interconnection in microelectronic packaging and market forces continue to drive toward finer pitch interconnections. In this paper, fine pitch flip chip (FPFC) interconnection technology (i.e., less than 60um pitch) will be described. Two types of 50um pitch bump (Au stud & Cu pillar) will be evaluated and two different flip-chip (FC) bonding methods will be studied. Package structures of bare die flip-chip CSP (chip scale package) and also over molded version will be studied for reliability performance and volume assembly fit. For characterization, structure analysis will be performed at each reliability read point. Finally this paper will conclude by identifying the most robust bonding method for the FPFC devices.

Semiconductor package and circuit board for making the package

Abstract: Disclosed herein are semiconductor packages and stacks thereof. An example package includes an insulative substrate having a first surface, first apertures, a second aperture, and circuit traces on the first surface. A first portion of each circuit trace overlies a first aperture and an end of the circuit trace is near the second aperture. A solder ball is in each first aperture, fused to the overlying circuit trace. A semiconductor die is in the second aperture and is electrically connected to the ends of the traces. A third aperture may extend through the first portion of each circuit trace. A second package can be stacked on a first package. Solder balls of the second package each fuse with an underlying solder ball of the first package through a third aperture of the first package. The dies of the stacked packages may be positioned for optical communication with each other.