Institution
Amkor Technology
Company•Tempe, Arizona, United States•
About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..
Topics: Semiconductor package, Substrate (printing), Die (integrated circuit), Layer (electronics), Flip chip
Papers published on a yearly basis
Papers
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06 Aug 2009TL;DR: In this paper, a stackable variable height via package with variable height vias is proposed, where the vias include a first via on the first surface of the substrate less than a height of the second via.
Abstract: A stackable variable height via package includes a substrate having a first surface and terminals thereon. The terminals include a first terminal and a second terminal. Vias are on the terminals, the vias including a first via on the first terminal and a second via on the second terminal. The first via has a height from the first surface of the substrate less than a height of the second via from the first surface of the substrate. The package further includes a package body and via apertures in the package body to expose the vias. Forming the stackable variable height via package with variable height vias readily accommodate stacking of additional packages having different types of terminals, e.g., LGA and BGA type packages, as well as variable degrees of warpage on the stackable variable height via package. Further, the vias are formed with a minimum pitch.
23 citations
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03 Dec 2008TL;DR: In this article, a shield spacer having a first and second surface is provided wherein the second surface of the shield is attached to a first surface of a first die and a plurality of wirebonds are attached to the shield and to the substrate.
Abstract: A semiconductor device has a substrate. A first die is electrically attached to a first surface of the substrate. A shield spacer having a first and second surface is provided wherein the second surface of the shield spacer is attached to a first surface of the first die. A plurality of wirebonds are attached to the shield spacer and to the substrate. A mold compound is provided for encapsulating the first die, the shield spacer, and the wirebonds.
23 citations
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03 Dec 2009TL;DR: Fan out buildup substrate stackable packages as discussed by the authors have an active surface having bond pads and a first die side buildup dielectric layer is applied to the active surface of the electronic component and to a first surface of package body.
Abstract: A fan out buildup substrate stackable package includes an electronic component having an active surface having bond pads. A package body encloses the electronic component. A first die side buildup dielectric layer is applied to the active surface of the electronic component and to a first surface of the package body. A first die side circuit pattern is formed on the first die side buildup dielectric layer and electrically connected to the bond pads. Through vias extend through the package body and the first die side buildup dielectric layer, the through vias being electrically connected to the first die side circuit pattern. The fan out buildup substrate stackable package is extremely thin and provides a high density interconnect on both sides of the package allowing additional devices to be stacked thereon.
23 citations
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29 Dec 2000TL;DR: In this paper, tools and methods for making molded optical integrated circuits including one or more waveguides are disclosed, and a molding die is provided that includes a substrate that has a topographically patterned first surface.
Abstract: Tools and methods for making molded an optical integrated circuit including one or more waveguides are disclosed. In one embodiment, a molding die is provided that includes a substrate that has a topographically patterned first surface. A conformal protective film is provided over the first surface of the substrate. The substrate may be formed of silicon or gallium arsenide, and may be patterned using conventional semiconductor patterning techniques, such as plasma etching. The protective film may be metal (e.g., nickel or titanium), diamond, or some other hard material. Typically, a plurality of such molding dies are formed from a wafer of the substrate material. The die is pressed into a moldable material, such as thermal plastic, to form the wave guide(s) of the optical integrated circuit. A plurality of the dies may be mounted around the curved surface of a heated roller, and a heated tape of the waveguide material may be fed under the roller in a mass production process. Alternatively, the die may be mounted in an injection molding cavity, and the IOC may be formed by an injection molding process.
23 citations
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13 May 2005TL;DR: In this paper, a semiconductor package and method for fabricating the same is disclosed, which includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls.
Abstract: A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin layer and a circuit pattern. The resin layer is provided with an opening at its center portion. The circuit pattern is formed on at least one of upper and lower surfaces of the resin layer and includes one or more bond fingers and ball lands exposed to the outside. The semiconductor chips have a plurality of input/output pads on an active surface thereof. The semiconductor chips are stacked at a position of the opening of the circuit board, with at least one of the chips being within the opening. Alternatively, both chips are in the opening. The electric connection means connects the input/output pads of the semiconductor chips to the bond fingers of the circuit board. The encapsulant surrounds the semiconductor chips so as to protect the chips from the external environment. The conductive balls are fusion-bonded on the ball lands of the circuit board.
23 citations
Authors
Showing all 1070 results
Name | H-index | Papers | Citations |
---|---|---|---|
Thomas P. Glenn | 48 | 130 | 6676 |
Dong-Hoon Lee | 48 | 762 | 23162 |
Joungho Kim | 40 | 579 | 7365 |
Steven Webster | 34 | 83 | 3322 |
Young Bae Park | 33 | 216 | 4325 |
Roy Dale Hollaway | 28 | 53 | 2324 |
Ronald Patrick Huemoeller | 26 | 91 | 2385 |
Robert Francis Darveaux | 23 | 70 | 1881 |
MinJae Lee | 23 | 99 | 3083 |
Il Kwon Shim | 21 | 41 | 1403 |
Vincent DiCaprio | 20 | 27 | 1973 |
Sukianto Rusli | 19 | 44 | 1308 |
Glenn A. Rinne | 19 | 34 | 898 |
Ahmer Syed | 18 | 55 | 1192 |
David Jon Hiner | 18 | 54 | 1173 |