Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

A High-Power SOI-CMOS PA Module with Fan-Out Wafer-Level Packaging for 2.4 GHz Wi-Fi 6 Applications

Abstract: This paper presents the first high-power SOI-CMOS power amplifier (PA) embedded in a Fan-Out Wafer Level Package (FOWLP) and addressing 2.4 GHz Wi-Fi 6 applications. At 2.44 GHz, the PA delivers 35.1 dBm of saturated output power (P sat ) with 53% of peak PAE and 29.5 dB of power gain. Without DPD, the PA achieves state-of-the art measured performance with 26.5/24.5/21.9 dBm of linear output power (P out ) for an EVM (Error Vector Magnitude) of −30/−35/−43 dB with an operating current of 336/270/210 mA for MCS7/9/11 40MHz signals respectively. The PA shows robust operation under extreme load mismatch (8:1 VSWR) and temperature (-40 to 80°C) conditions.

Chip size image sensor wirebond package fabrication method

Abstract: To form an image sensor package, a window is mounted above an active area on an upper surface of an image sensor. A noncritical region of the upper surface of the image sensor is between the active area and bond pads of the image sensor. A lower surface of a step up ring is mounted above the noncritical region of the upper surface of the image sensor. An upper surface of the step up ring includes a plurality of electrically conductive traces. Bond wires are formed between the bond pads of the image sensor and the electrically conductive traces on the upper surface of the step up ring. The step up ring is mounted so that the window is located in or adjacent a central aperture of the step up ring.

Capacitor of semiconductor integrated circuit and method for manufacturing the same

Abstract: Provided are a capacitor of a semiconductor integrated circuit and a method for manufacturing the same, for example a metal-insulator-metal (MIM) type capacitor of a semiconductor integrated circuit, which is capable of improving adhesive force between an electrode layer and a dielectric layer of a capacitor, and a method for manufacturing the same. For example, the present disclosure provides a capacitor for a semiconductor integrated circuit having a new structure, which is capable of preventing a delamination phenomenon on an interface between a lower electrode layer and a dielectric layer by further forming a buffer layer, which is capable of decreasing or compensating for a difference in a coefficient of thermal expansion, between a metal electrode layer and a dielectric layer, particularly, between the lower electrode layer and the dielectric layer, and a method for manufacturing the same.

Plating Structure For Wafer Level Packages

Abstract: A plating structure for wafer level packages are disclosed and may include a semiconductor wafer comprising a plurality of semiconductor die and a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die. The plating structure may comprise a plating connection line around a periphery of the semiconductor wafer, and a plating bar coupling the plating connection line to plating traces on the plurality of semiconductor die. The plating traces may be electrically coupled to the redistribution layers on the plurality of semiconductor die. The semiconductor wafer may comprise a reconstituted wafer of said semiconductor die. The semiconductor wafer may comprise a wafer prior to singulating the plurality of semiconductor die. The plating bar may be located in a sawing line for the singulating of the plurality of semiconductor die. A passivation layer may cover the redistribution layer and the plating traces.

Method for fabricating a fan-in leadframe semiconductor package

Abstract: A semiconductor package comprising a plurality of elongate leads which each have opposed inner and outer ends, opposed first and second surfaces, and a third surface which is disposed in opposed relation to the first surface and recessed relative to the second surface. The second surface of each lead is positioned in close proximity to the inner end thereof. The third surface of each lead extends to the outer end thereof. A semiconductor die is attached to portions of the first surfaces of at least some of the leads. The semiconductor die is itself electrically connected to at least some of the leads. A package body covers the semiconductor die and the leads such that the second surfaces of the leads are exposed in a bottom surface of the package body and the outer ends of the leads are exposed in respective side surfaces of the package body.