Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Wafer level chip scale package and method of fabricating wafer level chip scale package

Abstract: A wafer level chip scale package includes a first dielectric layer having a first surface, a second surface, and a main through hole passing through the first dielectric layer between the first and second surfaces. A semiconductor die is disposed in the main through hole of the first dielectric layer and including a bond pad disposed away from the first surface of the first dielectric layer. A redistribution layer is electrically connected to the bond pad of the semiconductor die and extends along the second surface of the first dielectric layer. A second dielectric layer covers the first dielectric layer and the redistribution layer and has an opening exposing the redistribution layer. An under bump metal fills the opening of the second dielectric layer and is electrically connected to the redistribution layer. A solder ball is electrically connected to the under bump metal.

Semiconductor device having conductive wire with increased attachment angle and method

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

Decoupled Package-On-Package thermal characterization

Abstract: Thermal characterization of a Package-On-Package (PoP) presents a challenge due to the variation in stacking configurations. Currently available characterization methods as outlined in the JESD51 standard cannot predict die temperatures for packages with more than one die, let alone multiple stacked packages. A model is presented to predict die temperatures for PoP by combining individual resistor networks using a Delphi network modeling approach. Data from experimental tests were used to confirm the accuracy of a Finite element analysis (FEA) based conduction model for an assembled PoP under varying power combinations. Separate FEA models for top and bottom packages were used to extract resistance values for two different resistor networks. These network models were combined to predicted die temperatures with a difference less than 7% when compared to the FEA model of the PoP.

Embedded die in panel method and structure

Abstract: Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die.

Apparatus for manufacturing semiconductor packages

Abstract: A mold for manufacturing semiconductor packages, which allows leadframes to be easily separated from a top mold section after a molding process by utilizing eject pins therein. The mold includes a bottom mold section having housing parts on the upper surface so as to allow leadframes to be placed in a flat state therein, and a top mold formed with transports therethrough. The top mold also incorporates runners formed along a lower surface with connections to the transports to introduce encapsulation material into select regions. A plurality of gates and cavities for molding the semiconductor packages are in flow communication. The eject pins are reciprocally mounted in the top mold section contiguous with the runners thereof to facilitate separation of the leadframes from the top mold.