Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

MEMS packaging technology using a cavity structure for mass production

Abstract: Lower cost package for microelectromechanical systems (MEMS) have been required, because the cost portion of the MEMS package is more than 30% of the cost of a MEMS product For the reason, cost effective MEMS packaging platforms are proposed in this paper for high volume production Two package platforms are developed using an epoxy molding compound (EMC) onto copper (Cu) pre-plated lead frames (L/F) One is a cavity wall type with attaching a flat lid The other is an in-frame type with attaching a folded cap lid Finite element method (FEM) numerical modeling is performed to anticipate the mechanical warpage and stress of the packages The finally assembled packages are tested for wire pulling, lid pulling, hermetic test, and reliability tests The wire bonding strength was improved in about 40% using plasma cleaning before wire bonding Through a lid pulling test, the lid bonding strength of 240 kgf in average was obtained using an epoxy adhesive Finally, all samples of the packages passed the reliability tests of the TC, HAST and HST, standardized by JEDEC (joint electron device engineering council) Also, this cavity package showed excellent hermeticity through leak test

Wire bonding method and semiconductor package using the same

Abstract: PROBLEM TO BE SOLVED: To provide a wire bonding method together with a semiconductor package using it, where a die-to-die wire bonding is avoided to improve bonding yield for extended capillary life and reduced production cost. SOLUTION: There are provided a stage for providing a circuit board where, with a resin layer as a basic layer, a chip-mounting region where a semiconductor chip is mounted is provided at a center, and a multiple circuit patterns are formed at the outer perimeter of the chip mounting region, with a transfer pattern formed at the outer perimeter of the chip mounting region, a stage where multiple semiconductor chips are stacked and bonded in the chip-mounting region of the circuit board or multiple semiconductor chips are arrayed and bonded on a flat surface, a stage where the input/output pad of any one of semiconductor chips is bonded to the transfer pattern of circuit board using a conductive wire, and a stage where the input/output pad of another semiconductor chip, among the semiconductor ships, is bonded to the transfer pattern of circuit board using a conductive wire, so that the semiconductor chip, etc., is electrically continuous to each other via the transfer pattern.

Concentrated photovoltaic receiver package with stacked internal support features

Abstract: In accordance with the present invention, there is provided a CPV package which comprises a leadframe assembly, such leadframe assembly including multiple frames stacked on top of each other. A top frame of the leadframe assembly provides the electrical interconnect between the top or front surface of the receiver die and the bypass diode required to complete the circuit. The top frame also provides hook up wire interconnect pads for the completed CPV package. An exposed bottom surface of a bottom frame of the leadframe assembly defines a heat spreader which assists in thermal management. The fabrication of the CPV package to include multiple frames stacked on top of each other provides high thermal dissipation and high voltage isolation, while at the same providing a high level of reliability with a comparatively low manufacturing cost.

Packaging technique for a tunable miniature liquid iris operated by electrowetting actuation

Abstract: This paper presents a simple ultraviolet (UV) chemical sealant aided packaging technique for a tunable liquid iris actuated by electrowetting-on-dielectric (EWOD) principle. To evaluate the proposed UV chemical sealant aided packaging technique, a large number of tunable liquid iris samples (9×9×2 mm3) are prepared by standard MEMS fabrication processes. The optical functionality of the microfabricated tunable iris is firstly tested. When an electrical voltage is sequentially applied to patterned ITO electrodes inside the tunable iris, opaque liquid initially covering only in the rim of the iris shifts to the center of the iris, resulting that the aperture diameter of the iris is modified from 4.2 mm to 0.85 mm. To improve the packaging of the iris the optimum chemical sealant (TB3124M UV sealant, ThreeBond Inc.) is selected through heavy field tests of various chemical sealants. To verify the proposed packaging technique, the high thermal test of the iris with the UV chemical sealant aided packaging is conducted using a temperature chamber. The result shows that the iris with the UV chemical sealant aided packaging shows no liquid leakage and remains as it was, while the iris only with a mechanical packaging shows severe liquid leakage through the joint area of the iris. The proposed packaging is easy to use but provides reliable liquid packaging, which can be applied to various microfluidic devices without additional complicated microfabrication processes.

Semiconductor package with clip alignment notch

Abstract: An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed.