Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Effect of Electromigration-Induced Joule Heating on the Reliability of Sn-Ag Microbump with Different UBM Structures

Abstract: The effect of current stress-induced Joule heating on two different under-bump metallization (UBM) structures in Sn-Ag microbumps was investigated with current stressing at 150°C and a current density of 5 &!thinsp;× 104 A/cm2. Both Ni UBM and Cu UBM configuration microbump structures underwent extensive electromigration (EM) testing, with results revealing a longer lifetime with the Cu UBM configuration than the Ni UBM structure. The observed EM failure mechanism in the Ni UBM configuration was identified as a void formation within the bump interconnected Al trace and not due to damage accumulation inside the microbump structure. The intermetallic compound developed inside the microbump was formed and maintained its stability throughout the current stressing period. To identify the main driving force of damage accumulation in the Al trace, the current density and temperature distributions in the Sn-Ag microbumps were analyzed numerically via the finite element method. The simulation results showed higher Joule heating with the Ni UBM than the Cu UBM microbump configuration, along with the bump geometrical contribution of add-on higher Joule heating in the Ni UBM microbump structure.

Advances in WLCSP Technologies to Enable Cost-Reduction

Abstract: Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is su...

Apparatus and method for testing integrated circuit devices having contacts on multiple surfaces

Abstract: An apparatus and method which allows for testing a semiconductor device having contacts on multiple surfaces has a contactor assembly for holding a semiconductor device and for sending test signals from the test board to and from a first surface and a second surface of the semiconductor device. A latching device is removably coupled to the contactor assembly. The latching device is used to secure the semiconductor device to the contactor assembly and for sending test signals to and from the second surface of the semiconductor package to the contactor assembly.

Semiconductor device with increased I/O leadframe including passive device

Abstract: In accordance with the present invention, there are provided multiple embodiments of a semiconductor package, each embodiment including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, each embodiment of the semiconductor package of the present invention includes a generally planar die pad and a plurality of leads. Some of these leads include exposed bottom surface portions or lands which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. A passive device may be electrically connected to and extend between the die pad and one of the leads, and/or may be electrically connected to and extend between and adjacent pair of the leads.

Method for forming isolation trenches on a semiconductor substrate

Abstract: Disclosed is a method for providing an insulation trench on a semiconductor substrate. The method includes the steps of depositing a pad oxide layer and a nitride layer on a semiconductor substrate; etching the nitride layer and the pad oxide layer and depositing a first insulating layer; forming spacers along sidewalls of the pad oxide layer and the nitride layer by anisotropic etching the first insulating layer; forming trenches by etching the semiconductor substrate; forming a trench insulating layer pattern by depositing a second insulating layer and etching the same; and polishing the trench insulating layer pattern.