Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Enhanced chip scale package for wire bond dies

Abstract: A chip scale package assembly comprises an integrated circuit die wire bonded to a carrier for mounting to a printed circuit board. The carrier comprises top and bottom ground planes thermally and electrically bonded together by a number of grounded thermal vias. The top ground plane completely surrounds the wire bond signal connections made with the die, enhancing signal integrity. The top ground plane covers the die mounting area, providing grounding and heat spreading for the die. The thermal vias are also positioned in the mounting area, and thermally couple the die to the bottom-side ground plane. The bottom ground plane is positioned within a central area around which the signal connections from the top-side are arranged. Ground pads with attached solder balls are positioned within the bottom ground plane and conduct heat transferred from the die into a primary circuit board on which the carrier is mounted.

Substrate for semiconductor package and wire bonding method using thereof

Abstract: Disclosed is a substrate for semiconductor package and a wire bonding method using thereof. The substrate is provided with at least one reference mark on its surface to check a loading position and a shift state of a solder mask. The reference mark is composed of a combination of a reference pattern and a solder mask opening and is positioned in any location on an outer peripheral edge of a die attachment region. The reference mark may take various shapes. A method for checking a solder mask shift using the reference mark includes comparing a design value of the reference pattern and the solder mask opening with the reference pattern and the solder mask opening, which are formed in an actual material. After the solder mask shift is calculated, a wire bonding coordinate is newly constructed in consideration of the solder mask shift. This minimizes the wire bonding error.

Microstructure evolution in Cu pillar/eutectic SnPb solder system during isothermal annealing

Abstract: The reaction between Cu pillar and eutectic SnPb solder during isothermal annealing was studied systematically. Intermetallic compounds (IMCs), such as Cu6Sn5 and Cu3Sn, were formed in between Cu and SnThe parabolic rate law was observed on IMC formation, which indicated that the growth of IMCs was controlled by atomic diffusion (a diffusion-limited process). Annealing at 165 °C for 160 h decreased the growth rate of Cu6Sn5, and at the same time increased the growth rate of Cu3Sn. This was when Sn in solder was exhausted completely. The activation energies for the growth of Cu3Sn and Cu6Sn5 were measured to be 1.77 eV and 0.72 eV, respectively. The Kirkendall void that formed at the interface between Cu pillar and solder obeyed the parabolic rate law. The growth rate of the Kirkendall void increased when the Sn in solder was consumed in its entirety.

Method and apparatus for attaching multiple metal components to integrated circuit modules

Abstract: Apparatus for attaching multiple metal components to integrated circuit modules reduces manufacturing time for module assemblies having metal shields and/or heat sinks that must be applied to multiple modules within a manufacturing assembly. The metal components are manufactured in an array and the array assembly is attached to the integrated circuit substrate. The metal component array is then divided along with the modules after attachment. The modules are sawed apart before or after attachment. A reduction in manufacturing time is achieved through multiple placement of the metal components rather than individual placement.

Semiconductor device including leadframe with increased I/O

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die paddle and some of the leads being exposed in a common exterior surface of the package body.