Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Electronic package having flip chip integrated circuit and passive chip component

Abstract: A package includes both a flip chip mounted active Chip component and a passive chip component. The flip chip bumps between the bond pads of the active chip component and the substrate are low impedance. Further, by mounting the active chip component as a flip chip, the area on the substrate occupied by the active chip component is approximately equal to the area of the active chip component.

Alloying effect of Ni, Co, and Sb in SAC solder for improved drop performance of chip scale packages with Cu OSP pad finish

Abstract: While SAC305 and SAC405 have been shown to yield similar or better reliability than SnPb solder in temperature cycle test, it is becoming evident that the same Pb free solders perform poorly under drop/impact conditions. The primary reasons for this reduced performance are the lower ductility of solder and brittle IMC formation at CSP pad and solder interface. Although some improvements are possible by changing the pad finish from NiAu to Cu OSP, the performance is still not as good as NiAu-SnPb combination. In addition, Cu-Solder interface results in the formation of Cu3Sn intermetallic compound resulting in brittle interface as well as voiding within this IMC with aging. This study focuses on the alloying effect of Ni, Co, and Sb in SAC solder on the IMC formation and the drop performance of packages. The solder alloys considered had small % of either Ni, Co, or Sb added with varying basic composition of Sn, Ag, and Cu. A total of 6 alloys were evaluated against Sn3.0Ag0.5Cu solder alloy. The solder balls of each alloy were attached to packages with Cu OSP surface finish using standard package assembly process. The evaluation matrix included package and board level tests as well as interfacial IMC studies. The package level tests (ball shear, ball pull, and zone shear) and IMC studies were conducted on as-soldered and thermally aged samples. Board level drop tests were performed as per JESD22-B111 test method. The results show that changes in SnAgCu composition and the addition of some elements in SnAgCu based solder can significantly improve the drop performance, primarily because of differences in IMC formation and the strength of solder alloys. While lower Ag improves the ductility of solder itself, addition of minor % of Ni or Co retards the formation and growth of Cu3Sn intermetallic at pad-solder interface, thus minimizing the potential of void formation and failure at this IMC. It is shown that the drop performance of packages with Cu OSP (pad finish)-SnAgCuNi (solder) combination can be as good as or better than those with NiAu-SnPb combination

Wafer having alignment marks extending from a first to a second surface of the wafer

Abstract: A marked wafer includes a front-side surface and a back-side surface. A vertical scribe line and a horizontal scribe line are on the front-side surface of the wafer. A back-side alignment mark is located at an intersection of the vertical scribe line and the horizontal scribe line. The back-side alignment mark extends from the front-side surface to the back-side surface of the wafer. The back-side alignment mark is used to aligning a saw, which singulates the wafer from the back-side surface.

Optical device packages having improved conductor efficiency, optical coupling and thermal transfer

Abstract: An optical device package having improved conductor efficiency, optical coupling and thermal transfer, as well as various methods for packaging a semiconductor die provide reduced connection length, and improved optical and thermal characteristics. In one package, a conductive circuit pattern disposed on a transparent or translucent cover connects bond pads on the light receiving surface of the semiconductor die to external electrical contacts. The construction of the package reduces connection length and eliminates the air gap between the glass and the die. In another package, a substrate having a protruding wall supports the glass and the substrate provides an electrical connection to terminals for connection to an external device. In another package, the glass is supported by a die mounting board that supports the semiconductor die and includes leads for connection to an external device. In other packages, the glass is supported directly by the semiconductor die and the die is supported by an encapsulated assembly including leads that support the semiconductor die.

Stackable semiconductor package and manufacturing method thereof

Abstract: A stackable semiconductor package is disclosed that includes a semiconductor die coupled to a metal leadframe. The semiconductor die is coupled to a die pad and is electrically coupled to leads of the leadframe. The semiconductor die, the die pad, and an inner lead portion of each of the leads is embedded in an encapsulant, and an outer lead portion of each of the leads is free of the encapsulant. A surface of the die pad and of the inner lead portion of each of the leads is exposed in a plane with an exterior first surface of the encapsulant. The outer lead portion is vertically such that a mounting surface of the outer lead portion is provided below an opposite second surface of the encapsulant. Other semiconductor packages or electronic devices may be stacked on and electrically coupled to the exposed surface of the inner lead portions.