Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

A semiconductor package having an etched groove for an embedded device formed on bottom surface of a support substrate and a method for fabricating the same

Abstract: A semiconductor device with etched grooves for embedded devices is disclosed and may, for example, include a substrate comprising a top surface and a bottom surface, a groove extending into the substrate from the bottom surface, and a redistribution structure in the substrate between the top surface and the bottom surface of the substrate. A semiconductor die may, for example, be coupled to the top surface of the substrate. An electronic device may, for example, be at least partially within the groove and electrically coupled to the redistribution structure. A conductive pad may, for example, be on the bottom surface of the substrate. A conductive bump may, for example, be on the conductive pad. The electronic device in the groove may, for example, extend beyond the bottom surface of the substrate a distance that is less than a height of the conductive bump from the bottom surface of the substrate. An encapsulant may, for example, encapsulate the semiconductor die and the top surface of the substrate. The electronic device may, for example, comprise a capacitor.

Stress relieving through-silicon vias

Abstract: Methods and systems for stress relieving through-silicon vias are disclosed and may include forming a semiconductor device comprising a stress relieving stepped through-silicon-via (TSV), said stress relieving stepped TSV being formed by: forming first mask layers on a top surface and a bottom surface of a silicon layer, forming a via hole through the silicon layer at exposed regions defined by the first mask layers, and removing the first mask layers. The formed via hole may be filled with metal, second mask layers may be formed covering top and bottom surfaces of the silicon layer and a portion of top and bottom surfaces of the metal filling the formed via hole, and metal may be removed from the top and bottom surfaces of the metal exposed by the second mask layers to a depth of less than half a thickness of the silicon layer.

Semiconductor device utilizing an adhesive to attach an upper package to a lower die

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die.

The study of bare-die FCBGA die damage in response to applied mechanical stress during heat sink assembly

Abstract: Die chipping or cracking in bare-die FCBGA packages is occasionally but consistently reported by OEMs during system-level heat sink installation. Since heat sink assembly is often a manual process, it can be difficult to determine if the damage was the result of a latent component defect or was induced during heat sink assembly. Most heat sinks require some type of spring force to maintain sufficient mechanical contact with the target electrical component, such as spring-loaded push-pins or Z-clips. When installed properly, these spring systems will not damage the electrical component. However, if the heat sink was installed improperly (i.e., tilted, with excessive force, etc.), or if the full spring deflection is maxed out, die damage may occur. Published studies on this topic are limited, so the following analysis was conducted. In this study, a test method was developed to exert a repeatable, controllable force on the top of a bare-die BGA component. The force was varied in magnitude, load/impact angle, and load rate. In addition, criteria for systematically characterizing component damage response were developed. Based on the data collected, the authors were able to characterize and compare the propensity to create damage by different types of assembly forces, such as forces perpendicular to the component, off-angle, excessive, slow, etc. Detailed quantitative results are presented. The test methods and empirical data generated during this study are useful in identifying certain limits in procedures used for system-level heat sink assembly that should result in less component damage and higher yields.

Substrate reaches substrate including cross tie part

Abstract: The utility model provides a substrate reaches substrate including cross tie part. The utility model provides an including the substrate of cross tie part, wherein the cross tie part include along the marginal cross tie part at the edge of substrate, just in the edge at least one is the nonlinearity. The announcement of provide for being used for optimizing the semiconductor device's on chip / substrate figure. Optimization including efficiency arrange, cut and pack the device.