Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Semiconductor package including heat sink with layered conductive plate and non-conductive tape bonding to leads

Abstract: A semiconductor package provided with a heat sink adapted to discharge heat from the package. The package has an oxidation film formed on an upper surface portion of the heat sink to which a semiconductor chip is attached, thereby improving the bonding between the semiconductor chip and heat sink to prevent the occurrence of an interface peel-off and the formation of cracks. This results in an improvement in reliability. A silver layer or a double layer consisting of a nickel layer and a palladium layer formed over the nickel layer is plated on the remaining upper surface portion of the heat sink not attached with the semiconductor chip. Accordingly, it is also possible to achieve easy ground bonding and power bonding. This results in an improvement in performance of the finally produced semiconductor package.

Thin image sensor package

Abstract: A thin image sensor package includes an image sensor having an active area which is responsive to radiation. The image sensor is mounted to a substrate which is transparent to the radiation. The image sensor is mounted such that the active area of the image sensor faces the substrate. Of importance, the substrate serves a dual function. In particular, the substrate is the window which covers the active area of the image sensor. Further, the substrate is the platform upon which the image sensor package is fabricated. As a result, the image sensor package is thin, lightweight and inexpensive to manufacture.

Plastic integrated circuit device package and method of making the same

Abstract: A package for an integrated circuit device, having a die, a die pad, leads, bond wire, and an encapsulant. The lower surfaces of the die pad and the leads are provided with stepped profiles. Structures extending from lateral sides of the leads are formed to prevent the leads from being pulled horizontally from the package. Encapsulant material fills beneath the recessed, substantially horizontal surfaces of the die pad and the leads, and thereby prevents the die pad and the leads from being pulled vertically from the package body. Other portions of the die pad and the leads are exposed within the package for connecting the package externally.

Thermal via heat spreader package and method

Abstract: A thermal via heat spreader package includes an electronic component having an active surface including a nonfunctional region. A package body encloses the electronic component, the package body comprising a principal surface. Thermal vias extend from the principal surface through at least a portion of the package body and towards the nonfunctional region. A heat spreader is thermally connected to the thermal vias. Heat generated by the electronic component is dissipated to the thermal vias and to the heat spreader. The density of the thermal vias is increased in a hotspot of the electronic component thus maximizing heat transfer from the hotspot. In this manner, optimal heat transfer from the electronic component is achieved.

Wafer level production of chip size semiconductor packages

Abstract: The invention provides a manufacturing process for making chip-size semi-conductor packages (“CSPs”) at the wafer-level without the added size, cost, and complexity of substrates in the packages or the need to overmold them with plastic. One embodiment of the method includes the provision of a semiconductor wafer with opposite top and bottom surfaces and a plurality of dies integrally defined therein. Each die has an electronic device formed in a top surface thereof, and one or more electrically conductive vias extending therethrough that electrically connect the electronic device to the bottom surface of the die. The openings for the vias are formed ablatively with a laser and plated through with a conductive material. In a BGA form of the CSP, the vias connects the electronic device to lands on the bottom surface of the die. The lands may each have a bump of a conductive metal, e.g., solder, attached to it that functions as an input-output terminal of the CSP. When fabrication of the wafer is complete, the finished packages are singulated from the wafer using conventional wafer cutting techniques.