Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Wafer level fan-out package with a fiducial die

Abstract: A wafer level fan-out package with a fiducial die is disclosed and may include a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin, passivation layers on an upper surface and a lower surface of the molding compound resin except where redistribution layers are formed on upper and lower surfaces of the molding compound resin, and a metal pattern on a lower surface of the transparent fiducial die that is visible through an exposed upper surface of the transparent fiducial die. The pattern may comprise a standard coordinate for forming a through mold via utilizing laser drilling.

Microcircuit die-sawing protector

Abstract: A method and apparatus for protecting hypersensitive microcircuits on the face of a semiconductor wafer from contamination and mechanical damage during die sawing and subsequent die handling operations include the provision of a plastic sheet having an array of protective domes formed into it, the array corresponding to the array of microcircuits on the wafer, and the temporary adhesion of the sheet to the face of the wafer such that each die in the wafer is covered by a respective one of the domes, with an associated one of the microcircuits protectively sealed therein. Die sawing is performed with the component side of the wafer facing up, the cut passing between the domes and through the thicknesses of both the domed sheet and the wafer such that each die is separated from the wafer, with a corresponding one of the domes still attached to it. The domes may be removed later when the dies are located in a more benign environment by simply peeling them off the die. The invention enables the use of conventional die-handling equipment and results in improved device yield.

Leadframe having a mold inflow groove and method for making

Abstract: A leadframe having a mold inflow groove provides for an increase in the number of inner leads for connecting with outer electrical sources and accurate singulation. A molding compound is introduced through mold inflow grooves positioned at both sides of a tie bar into the cavity so that no culls remain on the tie bar after molding. The end of a runner of the mold die is positioned at a sufficient distance away from the molding area of the leadframe to allow the top and bottom surfaces of the tie bar to remain free of culls.

Cohesive-Zone Explicit Submodeling for Shock Life-Prediction in Electronics

Abstract: Modeling transient-dynamics of electronic assemblies is a multiscale problem requiring methodologies which allow the capture of layer dimensions of solder interconnects, pads, and chip-level interconnects simultaneously with assembly architecture and rigid-body motion. Computational effort needed to attain fine mesh to model chip interconnects while capturing the system-level dynamic behavior is challenging. Product-level testing depends heavily on experimental methods and is influenced by various factors such as the drop height, orientation of drop, and variations in product design. Modeling and simulation of integrated circuit (IC) packages are very efficient tools for design analysis and optimization. Previously, various modeling approaches have been pursued to predict the transient dynamics of electronics assemblies assuming symmetry of the electronic assemblies. In this paper, modeling approaches to predict the solder joint reliability in electronic assemblies subjected to high mechanical shocks have been developed. Two modeling approaches are proposed in this paper to enable life prediction under both symmetric and anti-symmetric transient-deformation. In the first approach, drop simulations of printed circuit board assemblies in various orientations have been carried out using beam-shell modeling methodologies without any assumptions of symmetry. This approach enables the prediction of full-field stress-strain distribution in the system over the entire drop event. Transient dynamic behavior of the board assemblies in free and JEDEC drop has been measured using high-speed strain and displacement measurements. Relative displacement and strain histories predicted by modeling have been correlated with experimental data. Failure data obtained by solder joint array tensile tests on ball grid array packages is used as a failure proxy to predict the failure in solder interconnections modeled using Timoshenko beam elements in the global model. In the second approach, cohesive elements have been incorporated in the local model at the solder joint-copper pad interface at both the printed circuit board (PCB) and package side. The constitutive response of the cohesive elements was based on a traction-separation behavior derived from fracture mechanics. Damage initiation and evolution criteria are specified to ensure progressive degradation of the material stiffness leading to cohesive element failure. Use of cohesive zone modeling (CZM) enabled the detection of dynamic crack initiation and propagation leading to intermetallic compound (IMC) brittle failure in PCB assemblies subject to drop impact. Data on solder interconnect failure has been obtained under free-drop and JEDEC-drop test.

Semiconductor device with integrated heat distribution and manufacturing method thereof

Abstract: A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.