Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Enhancing overall system functionality and performance with the right packaging solutions

Abstract: Printed circuit boards (PCBs) are the essential parts to assemble modern electronic circuits The PCB design and development process has a direct impact on the system cost and time to market On average, companies report that PCB represents 31% of the overall product cost Today's electronic circuits and PCB designs are extremely complex Multi-level mistakes are inevitable during the design and development stages Cost reduction pressure is also limiting the designers in achieving their goals by reducing a few layers from their PCB stackup or adjusting and tweaking their designs A paradigm shift in PCB design is underway through partitioning and modularizing the system and circuits to reduce PCB size and complexity, shortens design to market time, and simplifies the overall supply chain In order to develop a superior product to fulfill a desired functions, good balance needs to be achieved among competing factors such as performance, cost, form factors, manufacturability, design, system flexibility, and supply chain management (Fig 1) A wireless system is usually comprised of several subsystems performing different functions For example, a typical handset system includes baseband, transceivers, main and diversity FEM, memories, power management, power amplifiers, antenna switch, duplexer filter, etc In this day and age, system integration is mandatory in order for end use products to offer superior and competitive products Compared to an SoC solution, system level integration at the packaging level may provide benefits such as cost effectiveness, flexibility, and a shorter development cycle A concurrent development methodology between device and package design will definitely help the industry to understand the nature of system integration on a package

Camera module having lens mount with ir filter

Abstract: An image sensor package includes an image sensor, a window, and a molding, where the molding includes a lens holder extension portion extending upwards from the window. The lens holder extension portion includes a female threaded aperture extending from the window such that the window is exposed through the aperture. A lens is supported in a threaded lens support. The threaded lens support is threaded into the aperture of the lens holder extension portion. The lens is readily adjusted relative to the image sensor by rotating the lens support.

Review on the high temperature warpage measurement using shadow moiré

Abstract: Recently, the members of Jedec committee tried to publish new warpage spec criteria for high temperature to reduce SMT quality issue (open/short) during the reflow on the purpose of the development and the qualification of a component In order to verify the repeatability and reliability of warpage data with shadow moire, the study on high temperature warpage measurement was performed From this study, it was found that the warpage could be changed by various measurement parameters such as ramp rate, sample preparation, setup condition even though the JEDEC (JESD22B112) and JEITA (ED-7306) specification was fully followed Finally, in this paper, we tried to suggest the best known method considering key experimental factors which could affect the warpage in view point of high temperature warpage measurement

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology

Abstract: The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules...

Method of forming a packaged semiconductor device using ganged conductive connective assembly and structure

Abstract: A method for forming packaged semiconductor devices comprises providing a first conductive frame structure The method includes coupling a second conductive frame structure to the first conductive frame structure to provide a first sub-assembly, wherein the second conductive frame structure comprises a plurality of interconnected conductive connective structures The method includes encapsulating the first sub-assembly with an encapsulating layer to provide an encapsulated sub-assembly The method includes removing joined conductive portions of the first conductive frame structure to form a plurality of conductive flank surfaces disposed on side surfaces of the encapsulated sub-assembly The method includes forming a conductive layer on the conductive flank surfaces The method includes separating the encapsulated sub-assembly to provide the packaged semiconductor devices each having portions of the conductive flank surfaces covered by the conductive layer