Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Solder attach film and method of forming solder ball using the same

Abstract: A solder attach film includes a first cover film, a flux layer, a solder layer, and a second cover film, and it can be treated or kept in a roll shape. A solder ball forming method using the solder attach film includes preparing a semiconductor package or a semiconductor die, adhering the solder attach film, gridding, and reflowing. In the solder attach film adhering operation, the first cover film and the second cover film are removed, and the flux layer is adhered to electrically conductive pads of the semiconductor package or the semiconductor die. Subsequently, in the reflowing operation, the flux layer is volatilized and removed, and the solder layer is fused and fixed to the electrically conductive pads, so that solder balls are formed.

Semiconductor package having more reliable electrical conductive patterns

Abstract: A semiconductor package has a substrate comprising a resin layer of an approximate planar plate, a die pad coupled at a top surface of a center area of the resin layer and having a printed photo imaging type protective layer thereon and a plurality of electrically conductive patterns, on which the photo imaging type protective layer and a thermosetting protective layer are printed in a consecutive order, formed at a periphery of the die pad. A semiconductor die is coupled to the photo imaging type protective layer on the die pad of the substrate by an adhesive. A plurality of conductive wires is used for electrically connecting the semiconductor die to the electrically conductive patterns. An encapsulant is used for covering the semiconductor die, the conductive wires and the surface of thermosetting protective layer on the electrically conductive patterns in order to protect them from the external environment. A plurality of contacts are coupled to the electrically conductive patterns of the substrate.

Semiconductor package and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To make the thickness of a semiconductor package relatively thinner while the function and capacity of the package are improved by packaging many semiconductor chips in a laminated state. SOLUTION: A semiconductor package is constituted of a circuit board 10 on which a circuit pattern 19 containing bond fingers and ball lands, the connecting sections of which are opened from a coating, is formed on at least one of the upper and lower surfaces of a resin layer 11 having a central through section 16, at least two or more semiconductor chips 1 and 2 which are vertically laminated upon another and arranged in the through section 16 and carry many input-output pads (1a) and (2a) formed on their one surfaces, and electric connecting means 20 which connect the input-output pads of the semiconductor chips 1 and 2 to the bond fingers of the circuit board 10. The package is also constituted of a sealing section 30 which seals an area containing the semiconductor chips 1 and 2, connecting means 20, and through section 16 and many conductive balls 40 which are welded to the ball lands of the circuit board 10. At least one of the semiconductor chips 1 and 2 is positioned in the through section 16.

Edge mount semiconductor package

Abstract: A semiconductor package which is structured to allow for the edge mounting thereof in a vertical mount orientation. The semiconductor package comprises a flexible substrate or “flex circuit.” The flexible substrate includes a conductive pattern disposed on a first surface thereof, and a plurality of conductive pads or terminals disposed on a second surface thereof which is disposed in opposed relation to the first surface. Mounted to the first surface of the flexible substrate are one or more electronic components such as semiconductor dies. The semiconductor die(s) is/are electrically connected to the conductive pattern, and thereafter covered or encapsulated by a package body applied to a portion of the first surface of the flexible substrate. That portion of the flexible substrate including the conductive pads or terminals formed on the second surface thereof is thereafter folded and adhered to a portion of the package body through the use of a suitable adhesive.

The reliability performance of copper wire bonding BGA package by way of HAST methodology

Abstract: Cu wire bonding technology is increasingly being used for the various IC packages from consumer application to high-reliability electronic products due to cost reduction consideration as well as electrical and thermal performance improvement in comparison with Au wire bonding. Despite these positive impacts of the improvements, the reliability still needs to be correctly assessed by the industry in a quantitative manner due to uncertain materials and assembly process issue. In the study, multiple Cu wire types and wire bonding process conditions are designed to validate assembly integrity based on Lead free BGA package with 14×14 body size and 384 I/O. Two bonding wire manufacturers provide the copper wire and palladium coated copper wire used for evaluation. Green molding compound free of halogenated flame retardant with known chloride content is used to mold the BGA package. After process characterization is verified based on wire pull and bond shear test. A HAST methodology (Highly Accelerated Stress Test) is applied to validate the BGA package reliability for the understanding of corresponding materials interaction among the wire material, molding compound and bonding pad metallization due to the acceleration stress drive from the temperature and humidity and bias voltage. In this task, there are five HAST conditions executed including 130°C/85RH%, 130°C/55RH%, 110°C/85RH%, 120°C/60RH% and 85°C/85RH% under 5.5 volt bias. Various temperature and humidity represent relative stress factors to accelerate the test to fail, as well the 3 stress factors usually influence the ionic ingredient in the molding compound to react with Cu wire and pad metallization. There are 4 daisy chain loops designed to monitor electrical resistance after each time period set in one BGA package for the failure judgment when resistance is fully open. Base on the HAST result and following failure analysis, the effect of testing duration, temperature and humidity differences and mold compound type are discussed.