Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

A study on the effectiveness of dummy pattern design existence in multi-layer PBGA application

Abstract: In this paper, we will report our recent study results on the dummy pattern design effectiveness in multi layer PBGA (Plastic Ball Grid Array) packages focusing on final product quality of the semiconductor package. Until now, there is no experimental and empirical assessment on the effectiveness of dummy pattern existence which gives us the solid conviction in applying this concept in a high volume manufacturing scale in the PBGA industrial arena. This paper shows the detailed evaluation and experimental result with various design concepts of dummy patterns in multi layer PBGA substrates. From the thickness validation with same substrate manufacturing condition, to the overall PBGA package performance validation will be covered in this paper. Ball coplanarity and substrate thickness variation data will be reported with analytical simulation result.

Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die

Abstract: Semiconductor packages are disclosed One semiconductor package includes a semiconductor die with an active surface, an opposite inactive surface, and four peripheral side surfaces A substrate of the semiconductor package is coupled to one side surface of the semiconductor die Bond pads of the active surface are coupled to a substrate first surface that is coplanar with the active surface External interconnects, eg, solder balls, are formed on a second substrate surface that is perpendicular to the active surface An insulating layer, eg, an encapsulant, together covers the active surface and the substrate first surface An alternative semiconductor package includes two substrates, each attached to a respective one of two opposed side surfaces of the semiconductor die The remaining two side surfaces of the semiconductor die are exposed The external interconnects are formed on a third substrate surface that is coplanar with the inactive surface of the semiconductor die

Electronic component package fabrication method and structure

Abstract: An electronic component package includes a RDL pattern comprising a redistribution pattern terminal. A buildup dielectric layer is formed on the RDL pattern, the buildup dielectric layer having a redistribution pattern terminal aperture exposing the redistribution pattern terminal. An interconnection ball is formed within the redistribution pattern terminal aperture and on the redistribution pattern terminal. The interconnection ball includes an enclosed portion having an outer concave surface within the buildup dielectric layer. The angle of intersection between the outer concave surface of the interconnection ball and the redistribution pattern is less than 90°. This minimizes stress between the interconnection ball and the redistribution pattern which, in turn, minimizes failure of the bond between the interconnection ball and the redistribution pattern.

Semiconductor device with redistribution layers formed utilizing dummy substrates

Abstract: A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.

Board Level Reliability Study of Next Generation Large Die Wafer Level Chip Scale Package Structures

Abstract: Wafer Level Chip Scale Package (WLCSP) technologies are being used more often in electronic components due to their smaller size and lower cost, and are being applied to larger die and ball matrix sizes. Originally implemented mainly in mobile devices (i.e., smartphones), WLCSP components are now frequently used in new product categories that have more stringent use conditions than the mobile space. The harsher use conditions raise a concern of solder joint reliability, especially in temperature cycling due to the difference in the coefficient of thermal expansion between the silicon die and the laminate motherboard. While cycle life can be extended by using underfill, underfilling makes the surface mount assembly process more complex and costly, increases cycle time and inhibits rework. To solve the challenge of extending cyclic life without underfill, new WLCSP structures and materials have been proposed. This paper describes the investigation of some of these innovative solutions through motherboard assembly and board level reliability testing. The package variables consisted of two WLCSP structures utilizing ball support mechanisms and a Bismuth (Bi) bearing solder ball that is expected to increase fatigue life. Packages were produced separately with each variable, along with legs that included both new packages and new alloy. The finished assemblies, along with a control leg of standard structure/solder, were subjected to drop testing and temperature cycling. Solder joint integrity was monitored in-situ to accurately identify duration to failure for Weibull analysis. The results clearly show that this new generation of WLCSP structures can offer dramatically improved fatigue life without a significant sacrifice in drop reliability. This benefit should allow the use of WLCSPs in more challenging environments, as well as providing designers the option of using larger package sizes in existing mobile designs.