Institution
Amkor Technology
Company•Tempe, Arizona, United States•
About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..
Topics: Semiconductor package, Substrate (printing), Die (integrated circuit), Layer (electronics), Flip chip
Papers published on a yearly basis
Papers
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08 Dec 1999TL;DR: In this article, a window is placed in a pocket of the molding and a snap lid is secured in place Once secured, the snap lid presses against a peripheral region of an exterior surface of the window.
Abstract: An image sensor package includes a molding having a locking feature The package further includes a snap lid having a tab, where the tab is attached to the locking feature of the molding To form the image sensor package, a window is placed in a pocket of the molding The snap lid is secured in place Once secured, the snap lid presses against a peripheral region of an exterior surface of the window The window is sandwiched between the molding and the snap lid and held in place
54 citations
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04 Feb 2000TL;DR: In this paper, a substrate having a first surface with metal pads and lands thereon, and an opposite second surface having openings in it through which the metal pads are exposed is used to make low cost chip size semiconductor packages (CSPs).
Abstract: A method for making low cost chip size semiconductor packages (“CSPs”) includes preparing a substrate having a first surface with metal pads and lands thereon, and an opposite second surface having openings in it through which the lands are exposed. A solder mask is formed over the first surface of the substrate, and has apertures in it through which the metal pads are exposed. At least one vent opening is formed through the substrate and solder mask. A semiconductor die is electrically connected to the substrate through the apertures in the solder mask using the “flip chip” connection method. A body of an insulative plastic material is formed on the surface of the solder mask that simultaneously overmolds the die and underfills the space between the solder mask and the die in a single step. Solder balls are attached to the lands through the openings in the second surface of the substrate to serve as package input/output terminals.
54 citations
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13 May 2005TL;DR: In this article, a wafer level stacked package and its manufacturing method are discussed, where a first semiconductor die is electrically connected to an upper surface of a substrate and a second die is connected to a lower surface of the substrate.
Abstract: Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.
54 citations
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23 Mar 2001TL;DR: In this paper, two stacked semiconductor chips are encapsulated in a package body formed of an encapsulating material, and a portion of the second side of each lead is exposed at an exterior surface of the package body as an input/output terminal.
Abstract: Semiconductor packages are disclosed. An exemplary package includes horizontal leads each having a first side and an opposite second side. The second side includes a recessed horizontal surface. Two stacked semiconductor chips are within the package and are electrically interconnected in a flip chip style. One chip extends over the first side of the leads and is electrically connected thereto. The chips are encapsulated in a package body formed of an encapsulating material. The recessed horizontal surface of the leads is covered by the encapsulating material, and a portion of the second side of each lead is exposed at an exterior surface of the package body as an input/output terminal. A surface of one or both chips may be exposed. The stack of chips may be supported on the first side of the leads or on a chip mounting plate.
53 citations
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26 Jul 2001TL;DR: A ball grid array (BAG) package includes a substrate having a central aperture as mentioned in this paper, where traces are coupled to a lower surface of the substrate. Interconnection balls are formed on second ends of the traces.
Abstract: A ball grid array (BAG) package includes a substrate having a central aperture. Traces are coupled to a lower surface of the substrate. First ends of the traces support an electronic component in the central aperture. Interconnection balls are formed on second ends of the traces. The interconnection balls extend from the second ends of the traces, through the substrate, and protrude above a second surface of the substrate.
53 citations
Authors
Showing all 1070 results
Name | H-index | Papers | Citations |
---|---|---|---|
Thomas P. Glenn | 48 | 130 | 6676 |
Dong-Hoon Lee | 48 | 762 | 23162 |
Joungho Kim | 40 | 579 | 7365 |
Steven Webster | 34 | 83 | 3322 |
Young Bae Park | 33 | 216 | 4325 |
Roy Dale Hollaway | 28 | 53 | 2324 |
Ronald Patrick Huemoeller | 26 | 91 | 2385 |
Robert Francis Darveaux | 23 | 70 | 1881 |
MinJae Lee | 23 | 99 | 3083 |
Il Kwon Shim | 21 | 41 | 1403 |
Vincent DiCaprio | 20 | 27 | 1973 |
Sukianto Rusli | 19 | 44 | 1308 |
Glenn A. Rinne | 19 | 34 | 898 |
Ahmer Syed | 18 | 55 | 1192 |
David Jon Hiner | 18 | 54 | 1173 |