Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Package thermal challenges due to changing mobile system form factors

Abstract: Mobile platforms have driven semiconductor package form factors from several times the die area to sizes approaching die size. To make matters even more challenging, the package thickness, traditionally on the order of 1–3 mm, has been reduced to thicknesses less than 0.40 mm. In mobile applications, it is size that drives package design. There has been a price paid for the package shrinkage in terms of its thermal performance. Copper, previously used for power and ground planes, and multiple layers of traces, has been replaced with extremely fine traces built in fewer layers. The body size previously used to promote the spreading of heat from the die is now left with two options for heat flow: either out the top (immediately above the die) or through the bottom (below the die) of the package. Improvements to the chip architecture in terms of power efficiency is one of the few remaining options for thermal enhancement at the package-level. Further thermal enhancement should focus on the system level, as this is where the greatest opportunities exist. While many papers have focused on the thermal challenges associated with the system-level, few have translated these constraints to challenges at the package level. This study investigates the historical evolution of mobile platforms and their impact on packaging thermal challenges. Metrics for evaluating the optimization of packages for the mobile space will also be discussed.

Building Accuracies in Finite Element Models for Life Prediction of Solder Joints

Abstract: With the rapid transition to Pb free solder in electronic industry, reliability of solder joints and life prediction has seen a renewed interest. Using the knowledge gained from modeling SnPb solder, a number of life prediction models have been suggested for SnAgCu based solder joints. These models are determined utilizing certain modeling assumptions and material behavior. Assuming accuracy in test data, the methodology used for calculating the strain or energy density is a significant source of error which limits the application of life prediction model. Since measuring inelastic strain or energy density in a tiny solder joint is not practical, these values are usually calculated using analytical or numerical approach. All simulation approaches use some assumptions, which can impact the accuracy of life prediction model. For finite element analysis, these assumptions include factors such as the level of structural details, 2-D or 3-D representation, mesh density, boundary conditions, and material models used. This paper presents how these factors affect the accuracy and efficiency of finite element based simulations when applied for solder joint life prediction. The modeling approaches previously published for temperature cycling and drop/impact loading by the author have been reviewed and enhanced by using advanced simulation techniques. The effect of meshing, material properties, and solder behavior under slow and fast loading conditions are investigated.

Blind via capture pad structure fabrication method

Abstract: A capture pad structure includes a lower dielectric layer, a capture pad embedded within the lower dielectric layer, the capture pad comprising a plurality of linear segments. To form the capture pad, a focused laser beam is moved linearly to form linear channels in the dielectric layer. These channels are filled with an electrically conductive material to form the capture pad.

Development of high speed board level bend tester for drop impact applications

Abstract: Due to the widespread use of portable electronics, there is a significant increase in interest in exploring the impact reliability of electronic packaging during impact shock. Currently, the test standard used for board level drop testing is JESD 22-B111 [1], which specifies the impact pulse (i.e. 1500G at 0.5ms) as a criterion for drop testing. However, this may not mimic the actual product testing. The board level cyclic bend test standard (JESD 22-B113) [2] is subsequently developed and introduced to perform low frequency bending (1 to 3 Hz). However, cyclic bend at low frequency is not able to produce similar failure mode as drop testing because board frequency during drop impact is usually much higher. Thus in this study, a high speed bend test (>50Hz) is developed to perform strain-controlled bend testing. The strain amplitude and frequency effects on BGA and WLCSP package solder joint life on various board sizes and component layout are studied and discussed. An increase in frequency was found to result in a significant reduction in time to failure, though a shift in failure mode (from bulk solder to inter-metallic failure) and reduction in cycles to failure were not observed. Results indicated that at higher strain amplitudes, cycles to fatigue life of package significantly decreased. This study has also shown a certain extent of correlation between drop test and high speed bend test.

Fine pitch PoP introduction

Abstract: Package-on-package (PoP) has been widely adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. Typical PoP solution is applied to logic processor as bottom package and memory device as top package. TMV® solution is being applied to reduce the warpage and achieve the fine pitch PoP and stable stacking performance. Currently, 0.4mm MIF(Memory Interface Pitch) is the minimum pitch under production and more fine MIF pitch is being requested because more functions are being integrated on chip then chip size becomes larger even wafer node is going narrower. To sustain the similar package size with larger chip size, fine pitch PoP is required. In this paper, 0.3 and 0.27mm MIF pitch PoP will be studied as a solution for fine pitch PoP and as a interface material between Top and Bottom package, solder ball and Cu post will be evaluated.