Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Study of FC M BGA with low CTE core substrate

Abstract: Amkor's FCMBGA, flip chip package based on transfer molding for high performance device was developed and introduced to industry in 2008[1,2]. During the molding process, bump deformation was not significant, and voids were not observed under flip chip die. Coplanarity with a low Coefficient of Thermal Expansion, CTE, substrate construction was similar to a single piece lidded package construction. Coplanarity at high temperature did not change significantly with low CTE substrate compared to standard substrates. The flip chip package with molding passed reliability test such as Moisture Resistance Testing, MRT, and Thermal Cycling, TC 1500 cycles. No delamination or cracks were observed.

Direct-write wafer level chip scale package

Abstract: A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby avoiding the use of photoimagable materials and photo-etching processes.

Effect of Pb free Alloy Composition on Drop/Impact Reliability of 0.4, 0.5 & 0.8mm Pitch Chip Scale Packages with NiAu Pad Finish

Abstract: Recent industry data show that the drop/impact reliability of Chip Scale Packages has been detrimentally affected by switching to SAC alloys with Ag percent equal to or greater than 3%. The primary cause of this is attributed to the higher strength and lower ductility of SAC305 and SAC405 alloys compared to SnPb solder, resulting in higher stresses at IMC layers and causing interfacial failures. While previous study [1] focused on Cu OSP finish for the packages, the study reported here is a comprehensive collection of data for NiAu pad finish using various solder alloys. The alloys considered had Ag percent varying from 1.0 to 3.0%, Cu % from 0.1 to 0.7%, and small amount of Ni, In, Co, and Ge addition to the main SAC system. Metallurgical studies were performed on identifying the IMCs and their growth with time and temperature for these alloys. Additionally, a number of board level drop tests (JESD22-B111) were performed on 0.4, 0.5, and 0.8 mm pitch CSP devices using different ball sizes and solder alloys. Finally, the data was compared against the optimum Pb free alloy solution for Cu OSP substrates. The results show that while three element SAC alloy is sufficient of NiAu surface finish, the Ag content has to reduce to gain appreciable increase in drop performance. The effect of Cu % alone in solder alloy was not found to be significant for drop performance improvement. Also, the Sn1.2Ag0.5Cu0.05Ni alloy that worked best for Cu OSP finish [1] did not perform as good as Sn1.0Ag0.5Cu alloy for NiAu finish.

Circuit pattern tape for wafer-scale production of chip size semiconductor packages

Abstract: A circuit pattern tape for the wafer-scale production of chip size semiconductor packages is adapted to be laminated onto a semiconductor wafer and includes a flexible insulating layer, a plurality of identical circuit pattern units arrayed thereon, and a solder mask covering the circuit patterns. Each circuit pattern unit includes a central opening, a plurality of bond fingers arranged on opposite sides of the opening and electrically connected through the opening to associated die pads on an underlying semiconductor chip in the wafer, a plurality of solder ball lands, each having a solder ball attached thereto, and a plurality of conductive traces electrically connecting respective ones of the bond fingers and the solder ball lands to each other. The bond fingers and central opening are arranged so that they do not intersect singulation lines defining the coincident edges of the corresponding individual circuit pattern units and chips after they are cut from the wafer-tape assembly, thereby eliminating chipping of the wafer. The circuit pattern units may include a dummy pattern that is made of the same conductive metal as the solder ball lands, the conductive traces, and the bond fingers, and which is arranged on the circuit pattern to achieve a uniform distribution of the conductive metal thereon and thereby minimize voids between the tape and the wafer and bowing in the dissimilar materials of the tape due to a change in its temperature.

Wire bonding method and semiconductor package manufactured using the same

Abstract: A semiconductor package including plural semiconductor chips, and a wire bonding step for electrically interconnecting the semiconductor chips, are disclosed. In an exemplary method, a substrate is provided. Conductive circuit patterns are provided outside of a chip mounting region of the substrate, and conductive transfer patterns are provided proximate to the chip mounting region. Chips are placed in the chip mounting region. Conductive wires are bonded between input/output pads of a first chip and respective transfer patterns, and other conductive wires are bonded between input/output pads of a second chip and the same transfer patterns, thereby electrically connecting respective input/output pads of the two chips through a pair of bond wires and an intermediate transfer pattern.