Amkor Technology

About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Substrate (printing). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..

Method of forming trench for semiconductor device isolation

Abstract: A method of forming a trench for semiconductor device isolation includes the steps of making a trench at a device isolation area of a silicon wafer overlaid with a pad oxide and a nitride through photolithography and etching, forming a liner oxide at an inner wall of the trench, filling the trench through depositing an insulating layer onto the entire surface of the silicon wafer, densifying the insulating layer, and planarizing the densified insulating layer such that the insulating layer is left only at the inside of the trench. The step of forming the liner oxide includes the sub-steps of forming a first liner oxide through performing rapid thermal processing with respect to the silicon wafer with the trench, forming a second liner nitride on the first liner oxide through performing the rapid thermal processing with respect to the silicon wafer with the first liner oxide, and forming a third liner wet oxide on the second liner nitride through performing the rapid thermal processing with respect to the second liner nitride. The trench so formed has removed corners. The three rapid thermal processing may be performed in situ in a single rapid thermal processing machine without exposing the wafers to atmosphere.

Semiconductor package capable of die stacking

Abstract: A stackable semiconductor package. The semiconductor package comprises a plurality of first and second leads which are arranged in a generally quadrangular array having one pair of opposed sides defined by the first leads and one pair of opposed sides defined by the second leads. The first and second leads each include opposed, generally planar first and second surfaces, and a third surface which is also disposed in opposed relation to the second surface and positioned between the first and second surfaces. A first semiconductor die is electrically connected to the third surfaces of the first leads, with a second semiconductor die being electrically connected to the third surfaces of the second leads. A package body at least partially encapsulates the first and second leads and the first and second semiconductor dies such that the first and second surfaces of each of the first and second leads are exposed in the package body.

Moisture-resistant integrated circuit chip package and method

Abstract: A novel, moisture-resistant integrated circuit chip package is disclosed. In one embodiment, the integrated circuit chip package includes a rigid substrate having a chip side and a backside. A first conductive layer is formed on the chip side of the substrate, and has a pattern forming conductive traces. A first soldermask layer is formed on the chip side of the substrate. The first soldermask layer directly contacts the first conductive layer. The first soldermask layer has at least one opening formed therein. A first contact layer is formed over the first conductive layer in the opening of the first soldermask layer. A second conductive layer is formed on the backside of the substrate. A second soldermask layer is formed on the back side of the substrate and has at least one opening formed therein. A second contact layer overlies the second conductive layer in the opening of the second soldermask layer. The soldermask layer on the chip side of the substrate has high adhesion to the conductive layer, resulting in a high level of moisture resistance for the package.

Semiconductor package with warpage resistant substrate

Abstract: A semiconductor package and a method for fabricating a semiconductor package are disclosed. The semiconductor package includes semiconductor chip attached to a circuit board that includes at least one lateral slot formed through the circuit board. Provision of the slot reduces stresses in the circuit board that are manifested by warpage. The semiconductor chip may be positioned in a central aperture of the circuit board and held therein by hardened encapsulant material.

Circuit board for semiconductor package

Abstract: A circuit board for semiconductor package is designed to provide a complete grounding with corresponding equipment in the manufacture of the semiconductor package based on a circuit board, thereby preventing a breakdown of the circuit board or semiconductor chip caused by electrostatic charges. The printed circuit board for semiconductor package includes: a resinous substrate; a chip mounting region formed on the top surface of the resinous substrate for mounting a semiconductor chip thereon; a plurality of fine circuit patterns radially disposed in the circumference of the chip mounting region and extending to the edge of the chip mounting region; a plurality of ball lands formed in an array on the bottom surface of the resinous substrate, to be fused to conductive balls; a conductive via hole connecting the circuit patterns on the top surface of the resinous substrate to the ball lands on the bottom surface of the resinous substrate; a cover coat applied to the top and bottom surfaces of the resinous substrate to protect the circuit patterns from an external environment and make the ball lands open to the exterior; and a means for removing electrostatic charges provided at the edge of the substrate and connected to the plural circuit patterns to remove electrostatic charges in the manufacture of semiconductors.