Let C be an acyclic Boolean circuit with n gates and ≤ n inputs. A circuit manufacture error may result in a “Stuck-at” (S-A) fault in a circuit identical to C except a gate v only outputs a fixed Boolean value. The S-A fault simulation problem for C is to determine all possible (S-A) faults which can be detected (i.e., faults circuit and C would give distinct outputs) by a given test pattern input. We consider the case where C is a tree (i.e., has fan-out 1.) We give a practical algorithm for fault simulation which simultaneously determines all detectable S-A faults for every gate in the circuit tree C. Our algorithm required only the evaluation of a circuit FS(C) which has ≤ 7n gates and has depth ≤ 3(d + 1), when d is the depth of C. Thus the sequential time of our algorithm is ≤ 7n, and the parallel time is ≤ 3(d + 1). Furthermore, FS(C) requires only a small constant factor more VLSI area than does the original circuit C. We also extend our results to get efficient methods for fault simulation of oblivious VLSI circuits with feedback lines.

Computational Aspects of Vlsi

Efficient VLSI fault simulation

In this paper we consider some of the central issues involved in the design of parallel algorithms. We describe several efficient algorithms for idealised shared memory architectures and draw some conclusions as to what would be required to implement them on a realistic physical architecture, i.e. one with distributed memory. We also describe some systolic algorithms for matrix computations, sequence comparison and molecular modelling, and briefly discuss their implementation on arrays of transputers. In the final section we discuss the question of whether the current preoccupation with architectural details in parallel algorithm design is likely to persist. We briefly describe some techniques which show that a physically realistic general purpose parallel architecture based on distributed memory can be constructed which will execute any shared memory parallel algorithm with no significant overhead due to communication. We thus have the attractive prospect in the very near future of architectural independence in parallel algorithm design.

methods

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Parallel Algorithms and Architectures

Tight chip area lower bounds for string matching

The authors propose an algorithm for solving the channel routing problem that arises in QCL (quickly customized logic) technology. Routing in the upper and lower regions of the channel is handled by the algorithms UPPER and LOWER, respectively. All patterns are systematically examined one by one until a routing solution is found. Little computational time is used in determining the routability of each pattern. Consequently, the total running time is reasonable even when a large number of patterns are to be examined. Experimental results are given. >

A channel router for single layer customization technology

We describe total congestion 1 embeddings of complete binary trees into three dimensional grids with a fixed number of layers. More specifically, we give a one-to-one embedding of any complete binary tree into a hexahedron shaped grid such that no tree nodes or edges occupy the same grid positions. With 7 layers, the number of nodes in the grid is at most 1.09375 times the number of nodes in the tree and with 5 layers we obtain a ratio of 75/64=1.171875. Unlike more standard embeddings these embeddings intricately weave the branches of various subtrees into each other. Finally using a standard recursive method, for 2 layers a ratio of 39/32=1.21875 can be obtained.

Computational Aspects of Vlsi

Citations

Efficient VLSI fault simulation

Parallel Algorithms and Architectures

Tight chip area lower bounds for string matching

A channel router for single layer customization technology

Fixed layer embeddings of binary trees

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