In this work, we propose the use of two neural models performing jointly in order to minimize the same energy function. This model is focused on obtaining good solutions for the two pages book crossing problem, although some others problems can be efficiently solved by the same model. The neural technique applied to this problem allows to reduce the energy function by changing outputs from both networks -outputs of first network representing location of nodes in the nodes line, while the outputs of the second one meaning the half-plane where the edges are drawn.

Detailed description of the model is presented, and the technique to minimize an energy function is fully described. It has proved to be a very competitive and efficient algorithm, in terms of quality of solutions and computational time, when compared to the state-of-the-art methods. Some simulation results are presented in this paper, to show the comparative efficiency of the methods.

background

Computational Aspects of Vlsi

Two pages graph layout via recurrent multivalued neural networks

The multiple input multiple output (MIMO) detection problem of an uncoded system can be considered as a so-called integer least squares problem, which can be solved optimally with a hard-output maximum likelihood (ML) detector [1]. The ML detector solves optimally the so-called closest lattice point problem by calculating the Euclidean distances (EDs) between the received signal vector and points in the lattice formed by the channel matrix and the received signal, and selects the lattice point that minimizes the Euclidean distance to the received vector [2]. The ML detection problem can be solved with an exhaustive search, i.e., checking all the possible symbol vectors and selecting the closest point. The ML detector achieves a full spatial diversity with regard to the number of receive antennas; however, it is computationally very complex and not feasible as the set of possible points increases.

VLSI Implementations of Sphere Detectors

The starting points of this paper are two size-optimal solutions: (1) one for implementing arbitrary Boolean functions; and (2) another one for implementing certain subclasses of Boolean functions. Because VLSI implementations do not cope well with highly interconnected nets -- the area of a chip grows with the cube of the fan-in -- this paper will analyze the influence of limited fan-in on the size optimality for the two solutions mentioned. First, the authors will extend a result from Horne and Hush valid for fan-in {Delta} = 2 to arbitrary fan-in. Second, they will prove that size-optimal solutions are obtained for small constant fan-ins for both constructions, while relative minimum size solutions can be obtained for fan-ins strictly lower that linear. These results are in agreement with similar ones proving that for small constant fan-ins ({Delta} = 6...9) there exist VLSI-optimal (i.e., minimizing AT{sup 2}) solutions, while there are similar small constants relating to the capacity of processing information.

/pdf/small-fan-in-is-beautiful-4ah2zigpch.pdf

Small fan-in is beautiful

The development of a digital circuit synthesis program is described. The program accepts the transition table or a state machine and returns equations for an implementation that assumes a sum-of-product next-state and output functions. From the equations for the next-state and output functions, nMOS VLSI layout for a Weinberger array is generated. D flip-flops are assumed for memory elements. Using this tool, tedious manual calculations can be avoided and layouts can be generated automatically from state table descriptions.

State machine synthesis with Weinberger arrays

The development of parallel file rearrangement algorithms that simultaneously optimize both time and space is surveyed. The classic problem of merging two sorted lists is used to illustrate fundamental techniques. Recent implementations on real parallel machines are also discussed. A primary aim of this research is to help narrow the gap between the theory and practice of parallel computing.

Computational Aspects of Vlsi

Citations

Two pages graph layout via recurrent multivalued neural networks

VLSI Implementations of Sphere Detectors

Small fan-in is beautiful

State machine synthesis with Weinberger arrays

Time-Space Optimal Parallel Computation

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