: This is the final report on our work under ONR Contract N00D14-86-K-0726, August 1, 1986 through July 31, 1989. The major results are, in two areas: (1) Studies of systematic design procedures for a class of structured algorithms often encountered in signal processing applications. These are what we have called Regular Iterative Algorithms (RIAs) for which our results are summarized in Section 2. ( 2) The other major area of effort was the study of a notable family of algorithms that are not in the RIA form, viz., those associated with Viterbi decoding of convolutional and trellis codes or more generally with shortest-path problems in graphs. (MM)

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Computational Aspects of Vlsi

Systematic Methods for Design of VLSI Signal Processing Arrays for Communications Applications.

The paper presents a parallel scalable VLSI algorithms for solving the Dirichlet boundary value problem and the first biharmonic boundary value problem on a rectangle. The complexity parameters occurring in the VLSI model (area-A and time-T) are evaluated in dependence on the problem size n (the number of grid points in one direction) and the VLSI array size p (the number of processing cells in one direction). The algorithms presented have scalable properties, i.e. their designs are not limited to a fixed size of the problem but can be used to solve problems on n × n grid where (n − 1) = k(p − 1) for a chosen integerk≥1

Scalable poisson and vlsi biharmonic solvers

A nonlinear lower bound on the practical combinational complexity

Since the work of Kung, the systolic architectures have proven their efficiency to deal with many scientific algorithms (LU-decomposition, Gauss-Jordan elimination, ...). Since the early eighties, many works have been made in the area of automatic derivation of systolic architectures. In the general case, there are numerous solutions to the same problem. The final choice of the architecture is often done by comparison of performances. There are several criteria which can be considered: global time of computation, number of processors, latency of the circuit... In this article we are especially interested with the number of processors of the final architecture for which we present a heuristic method.

https://hal.inria.fr/inria-00074342/document

Optimization of Number of Processors in VLSI Arrays

The task of computing binary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing The paper describes a scalable VLSI architecture for the BPS problem The authors adopt as the central theme of this effort, the recognition of the fact that the broadcast delay incurred by a signal propagating along a bus is, at best, linear in the distance traversed Thus, one of the design criteria is to keep buses as short as possible In this context, the main contribution is to show that one can use short buses in conjunction with shift switching to obtain a scalable VLSI architecture for the BPS problem

Computational Aspects of Vlsi

Citations

Systematic Methods for Design of VLSI Signal Processing Arrays for Communications Applications.

Scalable poisson and vlsi biharmonic solvers

A nonlinear lower bound on the practical combinational complexity

Optimization of Number of Processors in VLSI Arrays

A scalable VLSI architecture for binary prefix sums

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