We analyze power--area--performance trade-offs within a hypothetical mesh-connected reconfigurable architecture. A new analytic model relating area, power, and performance based on a simple VLSI complexity metric, is used to determine the behavior of some computing functions mapped to the platform. Although it might reasonably be expected that entirely local connectivity in the array would impose severe delay overheads, thus making performance--power trade-offs more difficult, it was found that the flexibility of the reconfigurable platform, in which logic and interconnect are (mostly) interchangeable, can result in compact layouts, which tends to offset the impact of the interconnect delay.

methods

Computational Aspects of Vlsi

Power scalability in a mesh-connected reconfigurable architecture

background

http://www.control.ece.ntua.gr/papers/31.pdf

On the communication complexity of Lipschitzian optimization for the coordinated model of computation

Lower bounds on the area A(n,m,k,r) required for merging of two sorted sequences of k-bit numbers with length n and m respectively, when the inputs can be replicated up to r times (r ≤ n), are given: 

$$A\left( {n,m,k,r} \right) = \left\{ \begin{gathered}\Omega (\tfrac{n}{r}) for 2^k \geqslant \tfrac{n}{r} and n \geqslant m \geqslant \tfrac{n}{r} \hfill \\\Omega \left( {m\left( {\left( {\log \tfrac{n}{{rm}}} \right) + 1} \right)} \right) for 2^{\tfrac{3}{8}k} \geqslant \tfrac{n}{r} and \tfrac{n}{r} \geqslant m \hfill \\\Omega \left( {m\left( {\left( {\log \tfrac{{2^k }}{m}} \right) + 1} \right)} \right) for \tfrac{n}{r} \geqslant m and \tfrac{n}{r} \geqslant 2^{\tfrac{3}{8}k} and 2^{\left( {\tfrac{{3.\left( {8^K } \right) - 1}}{{8^{K + 1} - 1}}k} \right)} \geqslant m \hfill \\where K \geqslant 0 is the constant \hfill \\\end{gathered} \right.$$

Area complexity of multiconnective merging

The P-RAM model of computation has proved to be a very useful theoretical model for exploiting and extracting inherent parallelism in problems and thus for designing parallel algorithms. Therefore, it becomes very important to examine whether results obtained for such a model can be translated onto machines considered to be more realistic in the face of current technological constraints. 

In this thesis, we show how the implementation of many techniques and algorithms designed for the P-RAM can be achieved on the feasible SIMD class of computers. The first investigation concerns classes of problems solvable on the P-RAM model using the recursive techniques of compression, tree contraction and 'divide and conquer'. For such problems, specific methods are emphasised to achieve efficient implementations on some SIMD architectures. Problems such as list ranking, polynomial and expression evaluation are shown to have efficient solutions on the 2—dimensional mesh-connected computer. 

The balanced binary tree technique is widely employed to solve many problems in the P-RAM model. By proposing an implicit embedding of the binary tree of size n on a (√n x√n) mesh-connected computer (contrary to using the usual H-tree approach which requires a mesh of size ≈ (2√n x 2√n), we show that many of the problems solvable using this technique can be efficiently implementable on this architecture. Two efficient O (√n) algorithms for solving the bracket matching problem are presented. Consequently, the problems of expression evaluation (where the expression is given in an array form), evaluating algebraic expressions with a carrier of constant bounded size and parsing expressions of both bracket and input driven languages are all shown to have efficient solutions on the 2—dimensional mesh-connected computer. 

Dealing with non-tree structured computations we show that the Eulerian tour problem for a given graph with m edges and maximum vertex degree d can be solved in O(d√n) parallel time on the 2 —dimensional mesh-connected computer. 

A way to increase the processor utilisation on the 2-dimensional mesh-connected computer is also presented. The method suggested consists of pipelining sets of iteratively solvable problems each of which at each step of its execution uses only a fraction of available PE's.

On the implementation of P-RAM algorithms on feasible SIMD computers

Sequential computation is well understood but does not scale well with current technology. Within the next decade, systems will contain large numbers of processors with potentially thousands of processors per chip. Despite this, many computational problems exhibit little or no parallelism and many existing formulations are sequential. It is therefore essential that highly-parallel architectures can support sequential computation by emulating large memories with collections of smaller ones, thus supporting efficient execution of sequential programs or sequential components of parallel programs. 
This paper demonstrates that a realistic parallel architecture with scalable low-latency communications can execute large-memory sequential programs with a factor of only 2 to 3 slowdown, when compared to a conventional sequential architecture. This overhead seems an acceptable price to pay to be able to switch between executing highly-parallel programs and sequential programs with large memory requirements. Efficient emulation of large memories could therefore facilitate a transition from sequential machines by allowing existing programs to be compiled directly to a highly-parallel architecture and then for their performance to be improved by exploiting parallelism in memory accesses and computation.

Computational Aspects of Vlsi

Citations

Power scalability in a mesh-connected reconfigurable architecture

On the communication complexity of Lipschitzian optimization for the coordinated model of computation

Area complexity of multiconnective merging

On the implementation of P-RAM algorithms on feasible SIMD computers

Emulating a large memory with a collection of small ones

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