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Computational Aspects of Vlsi
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The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.read more
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Optimizing programmable logic arrays using the simulated
TL;DR: In the paper the programmable logic array (PLA) topological optimization problem is dealt with using folding techniques and a PLA folding algorithm based on the method of simulated annealing is presented.
Journal ArticleDOI
Algorithms for the compilation of regular expressions into PLAs
TL;DR: The compilation of regular expressions into specifications for programmable logic arrays (PLAs) that will implement the required function is discussed, along with the advantages of each method.
Book
An introduction to processor-time-optimal systolic arrays
TL;DR: This work presents a technique for finding a lower bound on the number of processors needed to achieve a given schedule of an algorithm represented as a dag, and provides a time-minimal processor schedule that meets the computed processor lower bounds.
Proceedings ArticleDOI
Area Efficient VLSI Design with Cells of Controllable Complexity
TL;DR: A new, hybrid, architecture is presented which combines the advantages of a high wire organization with those of a nearest neighbor systolic organization for applications where there may be a large amount of data movement using VLSI.
Journal ArticleDOI
A systematic methodology for mapping DSP algorithms onto multilevel array architectures
TL;DR: A systematic graph-based methodology for designing systolic arrays, which can perform concurrently, is introduced, and the main feature of the proposed architectures is the significant reduction of the computation time of the algorithm.